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VHDL "EVENT" Problem

Altera_Forum
Honored Contributor II
1,904 Views

Hello, I'm a beginner for using Quartus II. I have an error in this VHDL code 

-------------------------------------------------------------------------------------- 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

 

 

entity Test is 

port(clk : in std_logic; 

preset : in std_logic; 

flag : in std_logic;  

out : out std_logic_vector(15 downto 0); 

done : out std_logic 

 

); 

end Test; 

 

 

architecture RTL of Test is 

signal d :std_logic_vector(15 downto 0); 

signal q :std_logic_vector(15 downto 0); 

signal I :std_logic_vector(15 downto 0) := "0111010101001101"; 

signal flag_sgl : std_logic ; 

signal done_sgl, VI, : std_logic; 

 

begin 

process(clk,flag) 

 

begin 

 

if(preset= '0') then  

flag_sgl <= '0'; 

done_sgl <= '0'; 

VI <= '1'; 

elsif (clk'event and clk='1') then  

VI <= '0'; 

 

if (flag_sgl = '1')then  

flag_sgl <= '0'; 

done <= not(done_sgl); 

done_sgl <= not(done_sgl); 

out <= q(15 downto 0); 

q <= d; 

 

end if; 

end if; 

 

if (flag'event ) then 

flag_sgl <= '1'; 

end if; 

end process ;  

------------------------ 

d(0) <= I(0) when VI = '1' else q(1) ; 

d(1) <= I(1) when VI = '1' else q(2) ; 

d(2) <= I(2) when VI = '1' else q(0) xor q(3) ; 

d(3) <= I(3) when VI = '1' else q(4) ; 

d(4) <= I(4) when VI = '1' else q(5) ; 

d(5) <= I(5) when VI = '1' else q(6) ; 

d(6) <= I(6) when VI = '1' else q(0) xor q(7) ; 

d(7) <= I(7) when VI = '1' else q(8) ; 

d(8) <= I(8) when VI = '1' else q(9) ; 

d(9) <= I(9) when VI = '1' else q(0) xor q(10); 

d(10) <= I(10) when VI = '1' else q(11) ; 

d(11) <= I(11) when VI = '1' else q(0) xor q(12); 

d(12) <= I(12) when VI = '1' else q(13) ; 

d(13) <= I(13) when VI = '1' else q(14); 

d(14) <= I(14) when VI = '1' else q(0) xor q(15); 

d(15) <= I(15) when VI = '1' else q(0); 

 

end architecture RTL; 

----------------------------------------------------------------------------------------- 

I got a problem in the "RED" color line. 

I would like "flag_sgl" change value to '1', everytime that input signal "flag" change its value. 

Are there any way for detecting "flag" changing without using 'EVENT? 

Thank you in advance ^^
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Altera_Forum
Honored Contributor II
1,007 Views

Using edge like that translates to clock port signal with its rules. Better detect change of value: 

 

inside process 

flag_d <= flag; 

if flag /= flag_d then 

... 

end if;
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Altera_Forum
Honored Contributor II
1,007 Views

process(preset, clk)

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