Re: VHDL signal assignment with the OTHERS keyword

Altera_Forum · ‎03-06-2009

I'm not sure I'm posting this in the right place but I want to assign an unsigned or std_logic_vector to the same type of a larger size.

Input is 8 bits wide, outputsignal is 32 bits wide and I want to assign inputsignal(7 downto 0) to outputsignal(23 downto 16) with all other bits (31 downto 24 and 15 downto 0) in output being '0'.

I've been trying to do this using the others keyword but I'm not quite sure how to do assignments like that with multiple bits at once.

So something like this:

outputsignal <= ((23 downto 16) => inputsignal(7 downto 0), others => '0');

but in a way that the compiler understands...

Altera_Forum · ‎03-07-2009

Here is one way:

outputsignal <= x"00" & inputsignal & x"0000";

Here is another:

outputsignal(31 downto 24) <= (others => '0');

outputsignal(23 downto 16) <= inputsignal;

outputsignal(15 downto 0) <= (others => '0');

Altera_Forum · ‎03-09-2009

Or you could write:

outputsignal <= (others => '0');

outputsignal (23 downto 16) <= inputsignal;

Altera_Forum · ‎03-09-2009

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Or you could write:

outputsignal <= (others => '0');

outputsignal (23 downto 16) <= inputsignal;

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Sorry, batfink, just short question,

the behaviour would be right regarding its original funtion?

Altera_Forum · ‎03-09-2009

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Sorry, batfink, just short question,

the behaviour would be right regarding its original funtion?

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Yes, but only if written inside a process. In that case the second line will override the assignments done in the first one.

Outside a process these two lines will generate a multiple drivers error from the synthesizer as they are concurrent.

Altera_Forum · ‎03-09-2009

Hi Frank

Daixiwen is correct - this works inside a process - sorry I should have said that. Basically in a process, the last assignment is the one that takes effect. The result of this is that you can make a default assignment right at the beginning of the process and then effect changes to the default with or without conditions.

e.g.:


process (set_to_ones, do_something_else)
begin
    output <= (others <= '0');
    if set_to_ones = '1' then
        output <= (others => '1'(;
    elsif do_something_else = '1' then
        output <= "1ZX0HL-U";
    end if;
end process;

Basically this means that if none of the if branches execute, then the (others => '0') assignment will be output; if one of the other signals is high then the default (others => '0') assignment is overwritten and has no effect.

Going back to baldur's query, if I write:


process
begin
     outputsignal <= (others => '0');
     outputsignal (23 downto 16) <= inputsignal;
end process;

then the (others => '0') gets assigned to all bits, but some bits have this overridden by the next statement. Bits 23 downto 0 never in effect see the '0' assigment.

Altera_Forum · ‎03-10-2009

Really thank baldur for your query,

Really thank Daixiwen and batfink for your patient answers.

Altera_Forum · ‎03-10-2009

Does outputsignal <= ((23 downto 16) => inputsignal(7 downto 0), others => '0'); work ?

I have similar assignments in one of my projects :


ES <= (  
         0 => ...,
         1 => 
         2 => 
         3 => 
         4 => 
         5 => 
         6 => 
         7 => 
         others => '-'
         );

others are assigned to "don't care"

It seems working.

Altera_Forum · ‎03-10-2009

Thank you, it clarified a part of what I was thinking.

Another take on this.

using ieee.std_logic_unsigned but could change to numeric_std if I needed.

I have inputs from another module:

signal timecounter: unsigned(31 downto 0);

signal period: unsigned(7 downto 0);

And a signal that is used for a schedule off the main timer.

signal nexttime: unsigned(31 downto 0;


process(clk)
  if(clk'EVENT and clk = '1') then
     if(timecounter = nexttime) then
        -- do stuff
        -- do more stuff
        -- This is where the problem begins, need to cast the period(7 downto 0) to (31 downto 0) somehow and shift it left by 24 bits.
        nexttime <= timecounter + period shifted left by 24 bits
     end if;
  end if;
end process;

One solution I can think of is to do an assignment as above with a variable in the process, and then use the variable in the add operation. I'm just wondering if there is a prettier way.

Altera_Forum · ‎03-10-2009

There are several options, this is one

nexttime <= timecounter + (period & x"000000");

Altera_Forum · ‎03-11-2009

Try this for size:

below your signal declarations add:

constant period_shift : unsigned (timecounter'length - period'length - 1 downto 0) := (others => '0');

this creates a vector of all zeroes whose length is determined by the length of timecounter and period- i.e. suppose you change periodto be 10 bits - this line stays the same.

Then in your process put:

nexttime <= timecounter + (period & periodshift);

Again if you change the range of period or timecounter then everything rolls through automatically and you don't have to update any other code.

Regarding mmTuschi's question:

--- Quote Start ---

Does outputsignal <= ((23 downto 16) => inputsignal(7 downto 0), others => '0'); work ?

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I think it works for individual bits but not for ranges like this - unless one of the more recent VHDL standards have changed this and I haven't noticed.

On a slightly different note, most people I know prefer numeric_std over std_logic_unsigned or signed - the latter two aren't actually IEEE packages but Mentor / Synopsis packages that have cheekily been compiled into the IEEE library. numeric_std is an IEEE standard.

Hope this helps.

Altera_Forum · ‎03-14-2009

Yeah that compiled at least, now I just gotta finish the rest of the design.

Thank you!