Hello Experts,
We are working on one project based on VMM methodology so to compile it we are using Questasim. But we are facing a problem to run it. First it wasn't getting a path for VMM. So I downloaded the vmm package(vmm-1.1.1a/ vmm-1.2.2b), set the environment to --- Quote Start --- setenv VMM_HOME /../../Desktop/vmm-1.1.1a/ --- Quote End --- and compiled my program by using following command: --- Quote Start --- vlog -sv +incdir+$VMM_HOME/sv +incdir+$VMM_HOME/sv/std_lib/vmm_str_dpi.c +incdir+$VMM_HOME/sv/std_lib/vmm_xvc_dpi.c top_sv.sv --- Quote End --- Now it compiles the program successfully but gives error during simulation. The error is: --- Quote Start --- ** Fatal: (vsim-3770) Failed to find user specified function 'vmm_str_match'. The search list was empty.# Using -sv_lib, -sv_root, and -sv_liblist arguments can provide a search list# FATAL ERROR while loading design# Error loading design --- Quote End --- for simulation we are using following command: --- Quote Start --- vsim -c top -do "run -all;quit" --- Quote End --- For compilation we also tried command given below: --- Quote Start --- vlog -sv +incdir+$VMM_HOME +incdir+/../../Desktop/program +define+vmm_NO_STR_DPI top_sv.sv --- Quote End --- But still it gives the same error. we are using Questa.6.6. Plz give me some idea to simulate it.链接已复制
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I don't think you'll find too many people using Questa on this forum.
Have you filed a service request with Mentor? http://supportnet.mentor.com/ Their support is really very good. --- Quote Start --- failed to find user specified function 'vmm_str_match'--- Quote End --- Did you look to see where this function is defined in the VMM source? Cheers, Dave
--- Quote Start --- This function is defined in vmm_log.sv file. which is in VMM standard library. But still it can't get it. --- Quote End --- Does vmm_log.sv get compiled into the 'work' library, or a named library, eg., 'vmm'? There is a -L option to vlog and vsim that can be used for library searches. Perhaps that is what you need. I'm not that familiar with SystemVerilog compilation, so have not had to deal with this problem, sorry. Cheers, Dave
Hi Dave,
I already make a work library using vlib command. After simulation one error is generated according to it i need to use -sv_lib, -sv_root, and -sv_liblist. But i don't know how to use it. -DrekuHi Dreku,
--- Quote Start --- By using -L switch in vsim, the error of vmm_str_match is removed but the design is not loading during simulation.--- Quote End --- What is the error message? Have you tried one of the examples from Mentor's Verification Academy? http://www.verificationacademy.com/ I suspect they have a forum there that might have users with a little more experience with Questa and the VMM (+ UVM + OVM) libraries If you can setup a small example SystemVerilog example, I can try simulating it with Modelsim-SE, I think I have all the Questa stuff supported, if not, I can download it from Mentor. Cheers, Dave
Hi Dave,
I tried one example from --- Quote Start --- systemverilog.in/method.php --- Quote End --- . But in this also we get a same problem that design is not loading as given below: --- Quote Start --- $ vsim -c -Lf top -do "run -all;quit" Reading /tools/mentor/questa6.6c/questasim/tcl/vsim/pref.tcl # 6.6c # run -all # no design loaded!# quit --- Quote End --- So if u have any idea then tell me or if u have any example program which is in running condition then please send me i will check it in Questasim. Thanks & warm regards, Dreku--- Quote Start --- if u have any example program which is in running condition then please send me i will check it in Questasim. --- Quote End --- This tutorial is written using SystemVerilog, you could try it: http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial Cheers, Dave
Hi Dave,
--- Quote Start --- This tutorial is written using SystemVerilog, you could try it: http://www.alterawiki.com/wiki/using...aster_tutorial (http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial) --- Quote End --- Actually simple system verilog program runs successfully in Questasim but in program using vmm methodology, design is not loading. Herewith I am sending you one example program please find it and check it out. Thanks and Regards, Dreku.We have a VMM 1.1.1a kit that runs with Questa located at out Verification Academy at verificationacademy.com/forum/uvmovm-kit-downloads-and-user-contributions-forum/kit-downloads-and-user-contributions/18257-ovm-uvm-download-kits Look for it towards the bottom of the page. There is also documentation and examples in the kit. If you need a later release of the VMM, you will need to contact Mentor directly.
A different Dave. P.S. My account does not allow me to post links, so you will need to add http : // in frontHi Dave,
I tried both the versions of vmm and followed steps given in readme.txt but its not working. I also tried vmm-1.2.2b but it gives same error. And i can't register in Mentor supportnet because it gives me an error. Regards, DrekuDid you try the verificationacademy.com site in the contributions section? That is separate from SupportNet. If you get an error, nobody can help you unless you tell us what the error is.
Hi Dave,
The error in registration is: --- Quote Start --- error Your SupportNet registration could not be processed at this time. message for users we cannot register (generally open door) Thank you for your interest in Mentor Graphics SupportNet electronic services. We regret we cannot register you for SupportNet. There may be certain access limitations due to the nature of our respective businesses. If you participate in our Open Door Program or another partner program, please review your third party partner agreement which may define support as "maintenance updates and hotline support". You are welcome to browse any public SupportNet information. If you have any additional questions about the terms and conditions of your Open Door or third party partner agreement, please don't hesitate to contact the Open Door Program Administrator by sending email to open_door@mentor.com. Thank you! Bonnie Yexley Open Door Program Administrator open_door@mentor.com --- Quote End ---Did you try the verificationacademy.com site in the contributions section? That is separate from SupportNet.
I tried for request new password (http://verificationacademy.com/user/register/academy/password) but i didn't get mail from verificationacademy so now i will try for contact us.
Hi Dreku,
--- Quote Start --- Actually simple system verilog program runs successfully in Questasim but in program using vmm methodology, design is not loading. Herewith I am sending you one example program please find it and check it out. --- Quote End --- I'm traveling this week and do not have access to my Modelsim-SE license manager. I'll take a look at this example when I get back. Post a new message next Monday if I haven't posted a response, and that'll remind me. Cheers, Dave