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I'm trying to change the simulation resolution from 1ps in Quartus Prime 17.0 Lite Edition to 10ps or 100ps. I changed the '-t' option in the vsim line in the simulation settings like this:
vsim -novopt -c -t 100ps -L maxv -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.myFile_vhd_vec_tst
onerror {exit -code 1}
vlib work
vcom -work work myCPLD.vho
vcom -work work testSPI.vwf.vht
vsim -novopt -c -t 1ps -L maxv -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.myCPLD_vhd_vec_tst
vcd file -direction myCPLD.msim.vcd
vcd add -internal myCPLD_vhd_vec_tst/*
vcd add -internal myCPLD_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { ] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
The last thing I see before it crashes is: # do myCPLD.do# ** Warning: (vlib-34) Library already exists at "work".# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016# Start time: 13:09:47 on Jun 21,2017# vcom -work work myCPLD.vho # -- Loading package STANDARD# -- Loading package TEXTIO
# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives# -- Loading package maxv_atom_pack# -- Loading package maxv_components# -- Compiling entity myCPLD# -- Compiling architecture structure of myCPLD
# End time: 13:09:48 on Jun 21,2017, Elapsed time: 0:00:01# Errors: 0, Warnings: 0# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016# Start time: 13:09:48 on Jun 21,2017# vcom -work work testSPI.vwf.vht # -- Loading package STANDARD
# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity myCPLD_vhd_vec_tst# -- Compiling architecture myCPLD_arch of myCPLD_vhd_vec_tst# End time: 13:09:48 on Jun 21,2017, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L maxv -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.myCPLD_vhd_vec_tst # Start time: 13:09:48 on Jun 21,2017# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.mycpld_vhd_vec_tst(mycpld_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading maxv.maxv_atom_pack(body)# Loading maxv.maxv_components# Loading work.mycpld(structure)# Loading ieee.std_logic_arith(body)# Loading maxv.maxv_io(behave)# Loading maxv.maxv_lcell(vital_le_atom)# Loading maxv.maxv_asynch_lcell(vital_le)# Loading maxv.maxv_lcell_register(vital_le_reg)# ** Warning: Design size of 140403 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.# Expect performance to be adversely affected.# after#31
# Simulation time: 225000 ps
# Simulation time: 225000 ps
# Simulation time: 225000 ps
# Simulation time: 225000 ps
# Simulation time: 225000 ps
# End time: 13:10:03 on Jun 21,2017, Elapsed time: 0:00:15# Errors: 0, Warnings: 1
Completed successfully.
**** Converting ModelSim VCD to vector waveform ****
Reading C:/....testSPI.vwf......
Reading C:/.....myCPLD.msim.vcd...
Processing channel transitions...
followed by a crash into Windows. Any clues? Do I need to change some other things in the simulation settings too? Thanks.
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