Verilog 2005 Module Synax: No localparam port declaration allowed!

[ArnovHnl]

Dear Intel,

It came to my attention when I tried some Verilog code, that Quartus synthesis and Modelsim do not deal with Verilog 2005 in the same way when it comes to defining local parameters in the port parameter declaration list.

The reason why I wanted this is very simple: To allow the specification of derived parameter values that make the port declaration as a whole easier to read, easier to maintain, and prevent derived values from being modified outside the module through the defparam keyword.

See this code:

`timescale 1ns / 1ps

module ADDER  #(
// Parameters.
parameter               WIDTH   = 8,
// Local parameters, derived values.
localparam              MSB     = WIDTH - 1)(
input   wire            C,
input   wire[MSB:0]     A, B,
output  reg [WIDTH:0]   Y);

always @ (posedge C) Y <= A + B;

endmodule

Quartus does not accept this code and says that localparam is not valid, and that only parameter is. It's been like this since Quartus 7.

ModelSim on the other hand supports this code. I've also tried this with the latest version of Vivado from AMD, having installed this only for this purpose. I used their old ISE for the CPLDs I have laying around. And their IDE supports this Verilog construct as well.

Then, I wanted to know, what does the standard actually say? So I went to find this IEEE Verilog language reference and found their IEEE 1364-2005 document: Title (ustc.edu.cn)

Upon examining this document I noticed an oddity with the parameter specifications. According to their document parameter is allowed in a module port list and as a module item. See A.1.3 parameter_declaration, while the local parameter is not allowed. Only now while looking up the document for the sections I now note that localparam_declaration is listed too, though for the module_or_generate_item. Parameter specification is declared through non_port_module_item. So, at first thought, I thought the document didn't refer to local parameters for the inside of a module. 

So anyways, I believe that the module_parameter_port_list should also include localparam_declaration as an option.

It is however possible to still get to use localparams for derived values outside of the port list, but then the ports must be just the portlist without structural modifiers where the structural attributes are added to the port(s) inside the module itself, after the localparam section.

This however causes duplicate maintenance of port identifiers which I personally do not want to use just because of that. Quartus however does accept this method.

Long story, but... could an update where localparam is allowed in a portlist be added to Quartus? Although I work with a Cyclone V device and that's supported up to only 20.1.1 I believe.

Thanks and regards,

Arno.

[ShengN_Intel · Accepted solution]

Sent you an email.

[ArnovHnl]

Hello Sheng N,

The solution you provided through e-mail works sufficiently save the footnote I told about in my email reply. Thank you for assisting with this issue.

Regards,

Arno.