Verilog Error

Altera_Forum · ‎12-03-2015

Could you please let me know how to declare a synthesizable array of constants? The constants are shown in the define directive. The below is giving an error. I am new to verilog .

Thanks

`define DATA_0 1

`define DATA_1 2

`define DATA_2 4

`define DATA_3 8

`define DATA_4 16

`define DATA_5 32

`define DATA_6 64

`define DATA_7 128

module IRC (......);

input x,y,z;

out alpha, beta;

reg alpha, beta;

reg [7:0] IDATA [31:0] = {DATA_0, DATA_1, DATA_2, DATA_3, DATA_4, DATA_5, DATA_6, DATA_7};

...

begin

....

endmodule

Altera_Forum · ‎12-03-2015

The trouble is not your defines. With Verilog, you cannot initialise a 2D array in that way.

You should instead use an initial block:


initial begin
    IDATA = DATA_0;
    IDATA = DATA_1;
    ...
end

Also, you appear to have only 8 initialisation values, but there are 32 elements in the array to be initialised.

Altera_Forum · ‎12-04-2015

also

you need apostrophe in front of define symbol.

like ...

IDATA[0] = `DATA_0;

Altera_Forum · ‎12-07-2015

Thanks, it helped me a lot.

I have prepared a script file and am now compiling the files. The commands in the script are as shown below

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AIC_package.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AICController.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/sim/AIC_tb.v"

# Modifying modelsim.ini

# Model Technology ModelSim PE vlog 10.1b Compiler 2012.04 Apr 27 2012

# ** Error: C:/work/aaa/bbb/ccc/ddd/xly/AICController.v(18): Cannot open `include file "C:/modeltech_pe_10.1b/uvm-1.1a/../verilog_src/uvm-1.1a/src/AIC_package.v".

# -- Compiling module AICController

I could not figure out why its not getting the include file AIC_Package.v

Altera_Forum · ‎12-14-2015

where did you put the file?

try ls command (or dir command in Windows)

if the path C:/modeltech_pe_10.1b/uvm-1.1a/../verilog_src/uvm-1.1a/src/AIC_package.v exists ore not?

Altera_Forum · ‎12-14-2015

source files are in C:/work/aaa/bbb/ccc/ddd/xly and testbench in C:/work/aaa/bbb/ccc/ddd/xly/sim.

C:/work/aaa/bbb/ccc/ddd/xly/AIC_package.v

C:/work/aaa/bbb/ccc/ddd/xly/AICController.v

C:/work/aaa/bbb/ccc/ddd/xly/sim/AIC_tb.v

The script is run from C:/work/aaa/bbb/ccc/ddd/xly/sim

The script contains the following

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AIC_package.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/AICController.v"

vlog -reportprogress 300 -work work "C:/work/aaa/bbb/ccc/ddd/xly/sim/AIC_tb.v"

vsim work.AIC_tb.

I am confused about this path. This does not exist. Actually the file AIC_package.v is never placed in the folder where ModelSim is reporting error. Its placed alongside its main file AICController.v in C:/work/aaa/bbb/ccc/ddd/xly.

Altera_Forum · ‎12-15-2015

you should try to create the folder and put the file "AIC_package.v "

I think then the simulation works.

just for now , that is enough for you isn't it?

try it anyway.

Altera_Forum · ‎12-15-2015

What folder to creat? if this is C:/work/aaa/bbb/ccc/ddd/xly, its already created. Also work directory is also created.

Altera_Forum · ‎12-16-2015

the folder you missed.

the message tells you "C:/modeltech_pe_10.1b/uvm-1.1a/../verilog_src/uvm-1.1a/src/AIC_package.v "

which means "C:/modeltech_pe_10.1b/verilog_src/uvm-1.1a/src/AIC_package.v "

I don't know why modelsim requires that path.

but the message tells you, you need it anyway.

just try it and research the reason in someday later.