Verilog, SV- data types confusion (logic, reg, wire...)

[Altera_Forum]

Hello, I am having some confusion in understanding the purpose and usage of some SV and verilog data types.  

 In verilog, what is the difference between wire and reg ? When driving a port or connection blocks/modules which one should I choose ? Does wire also has 4 states like reg ?  In SV, I believe reg and logic are identical. I came across a coding guideline pdf in web which suggests to use reg for sequential blocks and logic for combinational blocks. However, I am not sure why as logic and reg has identical behavior.   I would appreciate if someone can help me to understand this.

[Altera_Forum]

It's a bit of a mess. 

 "reg" and "logic" are the original Verilog types. "reg" can be assigned within from "always" blocks (weather they describe sequential or combinatory logic), and can only have one driver. "wire" are assigned with "assign" or a module port and can have multiple drivers.  "logic" is an addition in SystemVerilog. It can be driven from either "always", "assign" or module port but can't be driven by multiple drivers.  So, if restricted to Verilog, I'll use "reg" and "wire" according to the restrictions above. If I'm using SystemVerilog, I'll use "logic" for pretty much everything. I'll use "wire" when I need multiple drivers. Within a FPGA, there's zero place for that, I only use it for testbenches where I need to model a bus with multiple devices.

[Altera_Forum]

Verilog initially used the term "Register" for the reg data type. However, the 1364-2001 LRM began using the term "Variable" because these things did not always represent a synthesizable register in RTL. Verilog allows you to make procedural assignments to variables (and synthesis tools may further limit where you can make procedural assignments to variables) A variable behaves like a variable in any other programming language: you make an assignment to that variable, and the value of that assignment holds in the variable until the next procedural assignment. Variables of type reg have 4-states; 0, 1, X, and Z. 

 Wires or networks(nets) are continuously driven by the outputs of modules, primitives like nand gates and continuous assign statements. wires can have 0, 1 or more drivers, and can never be procedurally assigned. Verilog wires have a complex system for resolving multiple drivers based on 120 states/strengths. Anytime the value of a driver changes, Verilog has to look at the values of all the other drivers on the network and uses a built-in resolution function for determining the result. For example, if you have a pull-up driving a wire and and another continuous assignment driving a Strong-0, the wire will resolve to 0. If the continuous assigment starts driving a Z, the wire will go to the Pull-1 state.  The SUPERLOG language, which was the predecessor to SystemVerilog, created the logic datatype that was originally slightly different from reg in that it allowed a single continuous assignments to logic variables in place of any procedural assignments. With only one driver, no strengths or resolution functions are needed, and whatever strength is being driving to the variable will result in a simple 4-state value.  Eventually, the SystemVerilog committee decided to make reg have the exact same functionally logic and now the two terms are synonyms for each other. I would consider the term reg deprecated and all new SystemVerilog code should just use logic.

[Altera_Forum]

Here is a good paper by Stuart Sutherland on this topic that was presented last week in SNUG 2013: 

 http://www.sutherland-hdl.com/papers/2013-snug-sv_synthesizable-systemverilog_presentation.pdf http://www.sutherland-hdl.com/papers/2013-snug-sv_synthesizable-systemverilog_paper.pdf  Thanks, Evgeni

[Altera_Forum]

Thanks a lot :) It was really helpful.