Verilog code for ADC using DE1-SOC

[olcay]

Hello,

My project is to convert an analog signal to digital, and I’m using the DE1-SoC ADC for this purpose. I’m trying to achieve this using the code from this video, but despite using the same code as in the video, my dout value always remains constant, and therefore my dataout value does not change. How can I solve this? 

Example video Signal Tap Logic Analyzer

My ADC verilog code

`timescale 1ns / 10ps

module adcsignal(clk, sclk, din, dout, cs, count,dataout, clock_out,dataout2);

input clk;

output reg din;

output wire sclk;

input dout;

output reg cs;

output reg [11:0] dataout,dataout2;

reg [11:0] data_temp;

output reg clock_out;

reg ADD2,ADD1,ADD0;

output reg [3:0] count;

initial 

begin

count = 4'd0;

cs = 1;

ADD2 = 0;

ADD1 = 1;

ADD0 = 0;

clock_out = 0;

dataout = 12'd0;

dataout2 = 12'd0;

data_temp = 12'd0;

end

always @(negedge clk)

begin

if (count == 0)

begin

cs <= 0;

end

end

assign sclk = cs?1:clk;

always @(posedge clk)

begin

count <= count + 4'd1;

end

always @(posedge clk)

begin

case (count)

1: begin

din <= ADD2;

end

2: begin

din <= ADD1;

end

3: begin

din <= ADD0;

ADD1 <= !ADD1;

end

endcase

end

always @(posedge clk)

begin

case(count)

3:

begin

if (ADD1 == 1)

dataout <= data_temp;

else

dataout2 <= data_temp;

end

4: data_temp[11] <= dout;

5: data_temp[10] <= dout;

6: data_temp[9] <= dout;

7: data_temp[8] <= dout;

8: data_temp[7] <= dout;

9: begin data_temp[6] <= dout;

clock_out <= 1;

end

10: begin data_temp[5] <= dout;

clock_out <= 0; end

11: data_temp[4] <= dout;

12: data_temp[3] <= dout;

13: data_temp[2] <= dout;

14: data_temp[1] <= dout;

15: data_temp[0] <= dout;

endcase

end

endmodule

[FvM]

Hi,

LTC2308 doesn't run without operating CONVST pin. It's also necessary to select an input channel via SDI (din) command.

You can refer to adc_ltc2308.v demonstration code. Or write your own code based on LTC2308 datasheet.

Regards
Frank

[olcay]

First of all, thank you for your response. There's something I don't understand. The DE1-SoC uses the AD7928 ADC, so why did you suggest using the LTC2308 instead?

[FvM]

Which DE1-SoC version you are talking about?

[olcay]

De1-SoC Cyclone V (5CSEMA5F31C6N)

[FvM]

There are 6 versions of DE1-SoC, you have apparently V1.

AD7928 requires CS edge to start conversion if I understand the datasheet right. Also useful channel selection.

[olcay]

How can I fix my code according to your suggestion? What should I add to the code and what should I change?

[FvM]

Hi,
presently CS isn't operated in the code (only written low but never high). It should however go high and low again between 16 clock pulses. I also wonder what's the clk frequency and how it's generated?

My preferred SPI template uses a single edge sensitive process clocked at 2*SCLK, generating all output signals including SCLK synchronously.

Regards
Frank

[ShengN_Intel]

Hi,

I had tested the terasic DE1-SoC CD-ROM design example DE1_SoC_ADC https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=4#contents

The ADC_SDO is transitioning correctly like the screenshot:

May be you can refer to the verilog file adc_ltc2308.v in the design example.

Thanks,

Regards,

Sheng

[olcay]

Hi,

I tried the example code you provided, but I encountered some errors. How can I resolve these?

Warning: DE1_SoC_QSYS.cpu: Nios II cores are not recommended for new projects and are subject to removal in a future release. Nios V cores are the recommended replacement as applicable.

Error (261005): Can't find the instance. Download a design with SRAM Object File containing this instance.

Thanks

[ShengN_Intel]

Hi,

Check the attached file.

Please program the .sof first and then program the .elf file. Then open .stp to view the waveform.

Program the .elf file:

1.Go to <path>/nios2eds/nios2_command_shell.sh to open nios ii shell

2.Run command nios2-download DE1_SoC_ADC.elf -c 1 -r -g

That is just a verilog module adc_ltc2308.v and being used in Nios II design.

Thanks,

Regards,

Sheng