Verilog coding issue

Altera_Forum · ‎05-31-2018

:confused::confused:Hello everyone

can some buddy guide me how initialize your own data set in verilog with complete sample example. I have written a code but getting error

module mean(A1,A2,A3,B1,B2,B3,C1,C2,C3,D1,D2,D3,M1,M2,M3);

input A1,A2,A3,B1,B2,B3,C1,C2,C3,D1,D2,D3;

output M1,M2,M3;

reg A1[50][1]='{51,49,47,46,50,54,46,50,44,49,54,48,48,43,58,57,54,51,57,51,54,51,46,51,48,50,50,52,52,47,48,54,52,55,49,50,55,49,44,51,50,45,44,50,51,48,51,46,53,50};

reg A2[50][1]='{70,64,69,55,65,57,63,49,66,52,50,59,60,61,56,67,56,58,62,56,59,61,63,61,64,66,68,67,60,57,55,55,58,60,54,60,67,63,56,55,55,61,58,50,56,57,57,62,51,57};

reg A3[50][1]='{63,58,71,63,65,76,49,73,67,72,65,64,68,57,58,64,65,77,77,60,69,56,77,63,67,72,62,61,64,72,74,79,64,63,61,77,63,64,60,69,67,69,58,68,67,67,63,65,62,59};

reg B1[50][1]='{35,30,32,31,36,39,34,34,29,31,37,34,30,30,40,44,39,35,38,38,34,37,36,33,34,30,34,35,34,32,31,34,41,42,31,32,35,36,30,34,35,23,32,35,38,30,38,32,37,33};

reg B2[50][1]='{32,32,31,23,28,28,33,24,29,27,20,30,22,29,29,31,30,27,22,25,32,28,25,28,29,30,28,30,29,26,24,24,27,27,30,34,31,23,30,25,26,30,26,23,27,30,29,29,25,28};

reg B3[50][1]='{33,27,30,29,30,30,25,29,25,36,32,27,30,25,28,32,30,38,26,22,32,28,28,27,33,32,28,30,28,30,28,38,28,28,26,30,34,31,30,31,31,31,27,32,33,30,25,30,34,30};

reg C1[50][1]='{14,14,13,15,14,17,14,15,14,15,15,16,14,11,12,15,13,14,17,15,17,15,10,17,19,16,16,15,14,16,16,15,15,14,15,12,13,14,13,15,13,13,13,16,19,14,16,14,15,14};

reg C2[50][1]='{47,45,49,40,46,45,47,33,46,39,35,42,40,47,36,44,45,41,45,39,48,40,49,47,43,44,48,50,45,35,38,37,39,51,45,45,47,44,41,40,44,46,40,33,42,42,42,43,30,41};

reg C3[50][1]='{60,51,59,56,58,66,45,63,58,61,51,53,55,50,51,53,55,67,69,50,57,49,67,49,57,60,48,49,56,58,61,64,56,51,56,61,56,55,48,54,56,51,51,59,57,52,50,52,54,51};

reg D1[50][1]='{02,02,02,02,02,04,03,02,02,01,02,02,01,01,02,04,04,03,03,03,02,04,02,05,02,02,04,02,02,02,02,04,01,02,02,02,02,01,02,02,03,03,02,06,04,03,02,02,02,02};

reg D2[50][1]='{14,15,15,13,15,13,16,10,13,14,10,15,10,14,13,14,15,10,15,11,18,13,15,12,13,14,14,17,15,10,11,10,12,16,15,16,15,13,13,13,12,14,12,10,13,12,13,13,11,13};

reg D3[50][1]='{25,19,21,18,22,21,17,18,18,25,20,19,21,20,24,23,18,22,23,15,23,20,20,18,21,18,18,18,21,16,19,20,22,15,14,23,24,18,18,21,24,23,19,23,25,23,19,20,23,18};

endmodule

:confused:

thanks in advance

Altera_Forum · ‎05-31-2018

What error are you getting? You've defined the inputs and outputs as single bit, but it seems like you're trying to create each as a 50 element memory?

Altera_Forum · ‎05-31-2018

I am getting syntax error though I tried my best to remove it but could not so can give me complete sample example like that which is synthesizable.

thanks

Altera_Forum · ‎05-31-2018

yes wanna to creat 50 element memory

Altera_Forum · ‎05-31-2018

Couple of different ways to do it, either all in verilog or with using a text file to init the memory contents.

So you can do this in verilog to initialize the block memory device memdat from the contents of a file:


    reg    memdat;
    initial $readmemb("meminit.txt", memdat, 0, 4095);

where the file meminit.txt contains 4096 lines of data (in this case 12bit binary strings since I used $readmemb):


000000000000
011000110001
111111000001
...
111111111111

or instead of that initial block that uses an external text file, you could use plain old verilog assignment statements:


    initial
        begin
        memdat = 12'hFFF;
        memdat = 12'b0000_1111_0000;
        ...
        memdat = 12'd1234;
        end

or a more complex set of verilog code:


    initial
        begin : init_block
        integer i;
        for (i = 0; i < 4096; i = i+1) memdat = 12'h000;
        memdat = 12'd1234;
        ... etc
        end

Altera_Forum · ‎06-01-2018

thank you very much can you tell me text file can contain integers ? and what will be the path of text file?

Altera_Forum · ‎06-01-2018

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thank you very much can you tell me text file can contain integers ? and what will be the path of text file?

--- Quote End ---

The default location of the file will be in the current project directory.

As to other data formats the answer is there are two versions of the memory access function: $readmemb expects a binary string format, and $readmemh expects a hex string format. There is no version that will expect decimal strings, which I assume is what you mean by 'integer' format.