Verilog excess Three no out puts

Altera_Forum · ‎11-13-2013

I have lots of trouble with my code and no one to ask why. The outputs are X(do not cares). I'm not sure why

`timescale 1ns/ 1ns
module excess_three (W,R,clk,Reset);
input W;
input clk;
input Reset;
output  R;
reg R;
reg  State;
reg  NextState;
parameter  Start = 3'b000 ,CarryOne= 3'b101, NoCarryOne= 3'b001; 
parameter  CarryTwo= 3'b011, NoCarryTwo= 3'b111;
parameter  CarryThree= 3'b010, NoCarryThree= 3'b110;
 
always @ (W or State)
begin
     case (State)
			
    Start:      NextState = (W==1)? CarryOne:NoCarryOne;
	Start:	R=(W==1)? 1'b1:1'b1;
    CarryOne:   NextState = (W==1)? CarryTwo:CarryTwo;
	CarryOne: R=(W==1)? 1'b1:1'b0;
    NoCarryOne:  NextState = (W==1)? CarryTwo:NoCarryTwo;
	NoCarryOne: R=(W==1)? 1'b0:1'b1;
    CarryTwo:    NextState = (W==1)? CarryThree:NoCarryThree;    
	CarryTwo: R=(W==1)? 1'b0:1'b1;
    NoCarryTwo:  NextState = (W==1)? NoCarryThree:NoCarryThree;
	NoCarryTwo: R=(W==1)? 1'b1:1'b0;
    
   CarryThree:  NextState = (W==1)? NoCarryThree:3'bxxx;
	CarryThree: R=(W==1)? 1'b1:1'b0;
               
    NoCarryThree: NextState = (W==1)? Start:Start;
	NoCarryThree: R=(W==1)? 1'b1:1'b0;
	
endcase
end
always @ (posedge clk or negedge Reset)
begin   
    if (Reset==0)
        State <= Start;
     else 
        State <=NextState;
end
endmodule

this is my test bench


`timescale 1ns/ 1ns
module excess_three_TB;
reg  W;
reg clk;
reg Reset;
wire  R;
excess_three test(.W(W),.R(R),.clk(clk),.Reset(Reset));
initial 
begin# 0 clk=0;# 0 Reset=0;# 0 W=4'b0000;
end
always begin# 5 clk = !clk;# 5 W=4'b0001;# 5 W=4'b0010;# 5 W=4'b0011;# 5 W=4'b0100;# 5 W=4'b0101;# 5 W=4'b0110;# 5 W=4'b0111;# 5 W=4'b1000;# 5 W=4'b1001;# 5 W=4'b1010;# 5 W=4'b1011;# 5 W=4'b1100;# 5 W=4'b1101;# 5 W=4'b1110;# 5 W=4'b1111;
end
initial  begin
 $display("\t\ttime,\tW\tclk,\tReset,\tR");
 $monitor("%d,\t%b,\t%b,\t%b,\t%d",$time,W, clk,Reset,R);
end
initial # 165 $finish;
endmodule

Altera_Forum · ‎11-13-2013

You have a couple of issues going on.

In the test bench. W is changing but not clock. So you only get one clock edge per group of W. Is this what you intended?

In the source code:

R is never set, and since only 1 positive clock edge occurs, not all bits are configured.

Add R=4'd0;

right after the begin and before the case(state) statement.

the second issue is the structure of your case statement: You have:

Start:      NextState = (W==1)? CarryOne:NoCarryOne;
Start:	R=(W==1)? 1'b1:1'b1;

The second "Start" statement never is get ran, since it matches the first one and drops out. This needs to be written as:

Start:      begin
                  NextState = (W==1)? CarryOne:NoCarryOne;
                  R=(W==1)? 1'b1:1'b1;
              end

for all your case structure.

so the finished code should look like:


`timescale 1ns/ 1ns
module excess_three (W,R,clk,Reset);
input W;
input clk;
input Reset;
output  R;
reg R;
reg  State;
reg  NextState;
parameter  Start = 3'b000 ,CarryOne= 3'b101, NoCarryOne= 3'b001;
parameter  CarryTwo= 3'b011, NoCarryTwo= 3'b111;
parameter  CarryThree= 3'b010, NoCarryThree= 3'b110;
always @ (W or State)
begin
  R=4'd0;
  case (State)
    Start:      begin
                   NextState = (W==1)? CarryOne:NoCarryOne;
                   R=(W==1)? 1'b1:1'b1;
                end
    CarryOne:   begin
                   NextState = (W==1)? CarryTwo:CarryTwo;
                   R=(W==1)? 1'b1:1'b0;
                end
    NoCarryOne: begin
                   NextState = (W==1)? CarryTwo:NoCarryTwo;
                   R=(W==1)? 1'b0:1'b1;
                end
    CarryTwo:  begin
                  NextState = (W==1)? CarryThree:NoCarryThree;
                  R=(W==1)? 1'b0:1'b1;
               end
    NoCarryTwo:begin
                  NextState = (W==1)? NoCarryThree:NoCarryThree;
                  R=(W==1)? 1'b1:1'b0;
               end
   CarryThree: begin
                  NextState = (W==1)? NoCarryThree:3'bxxx;
                  R=(W==1)? 1'b1:1'b0;
               end
  NoCarryThree:begin
                  NextState = (W==1)? Start:Start;
                  R=(W==1)? 1'b1:1'b0;
               end
endcase
end
always @ (posedge clk or negedge Reset)
begin
    if (Reset==0)
        State <= Start;
     else
        State <=NextState;
end
endmodule

Altera_Forum · ‎11-14-2013

thank you very much at first i had if else statements then i switched to the conditional statement only because i was so lost. Is there any advantage to using if statements vs the conditional statements? setting the value changed my values to all ones and after what you said it makes me think its my test bench is now the problem. I'm going to work on that before i re-post with my fixed code.

Altera_Forum · ‎11-14-2013

Case statements are better than if's if you have more than just a few cases. IE for 1-3 statements, it's if's are fine, but for more than 3 or 4 branches, a case statement is better.

If then elses, are always priority logic. IE the first condition is the most likely to occur. With case statements, you have the options of using synthesis "pragmas" that allows the tool to reduce the logic required. This allows the logic to run faster and be smaller, but at the cost that the simulator may not simulate the design exactly anymore.

The two most commonly used pragmas are parallel_case and full_case. Where parallel_case treats all cases as having the same priority, so the normal top-down priority (if, then, else) style conditioning is removed. full_case is telling the tool there is no other cases possible. It reduces the decoder required for each of the valid cases, but if a case that wasn't defined appears in the logic, it may activate multiple case branches.

Look up these pragmas, and read about them. They are very useful, but also can cause problems if not used properly.

Pete