Vhdl

Altera_Forum · ‎06-12-2018

I need help with the following task in the VHDL program: Based on the DE2 development board, design a 4-bit Johnson counter. The meter's status is to be displayed on 4 7-segment LED displays (eg 1110). The change in the meter's status is taking place run automatically, e.g. every 1s. Develop a test environment for the designed system.

I need to combine these two codes into one? 4-bit Johnson counter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ring_counter is
Port( CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR( 3 downto 0 ) );
end Ring_counter;
architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector( 3 downto 0 ):= "0001";
begin
process( CLOCK, RESET )
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge( CLOCK ) then
     q_tmp( 1 ) <= q_tmp( 0 );
q_tmp( 2 ) <= q_tmp( 1 );
q_tmp( 3 ) <= q_tmp( 2 );
q_tmp( 0 ) <= q_tmp( 3 );
end if;
end process;
Q <= q_tmp;
end Behavioral;

Altera_Forum · ‎06-12-2018

Operate the 4 segment display 7

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_dek is port(
din: in std_logic_vector( 3 downto 0 );
clk: in std_logic;
bp: inout std_logic;
segm_o: out std_logic_vector( 6 downto 0 )
);
end lcd_dek;
architecture ar_dyn of lcd_dek is
signal segm: std_logic_vector( 6 downto 0 );
begin
with din select
--gfedcba
segm <= "0111111" when "0000", -- 0
"0000110" when "0001", -- 1
"1011011" when "0010", -- 2
"1001111" when "0011", -- 3
"1100110" when "0100", -- 4
"1101101" when "0101", -- 5
"1111101" when "0110", -- 6
"0000111" when "0111", -- 7
"1111111" when "1000", -- 8
"1101111" when "1001", -- 9
"0000000" when others; --
wygaszenie
segm_o( 0 ) <= segm( 0 ) xor bp;
segm_o( 1 ) <= segm( 1 ) xor bp;
segm_o( 2 ) <= segm( 2 ) xor bp;
segm_o( 3 ) <= segm( 3 ) xor bp;
segm_o( 4 ) <= segm( 4 ) xor bp;
segm_o( 5 ) <= segm( 5 ) xor bp;
segm_o( 6 ) <= segm( 6 ) xor bp;
bp <= clk;
end ar_dyn

I am asking you to check the correctness and help in this task

Altera_Forum · ‎06-13-2018

Hi,

--- Quote Start ---

I need to combine these two codes into one? 4-bit Johnson counter:

--- Quote End ---

1. Either you combine these two entities in one or instantiate the “lcd_dek” entity in “Ring_counter” entity with required signals/variables & component declaration.

2. Check the DE2 development board crystal frequency & write the vhdl code to step down the frequency up to few Hz then & then only you can observe the display.

3. Write the test bench & check functionality.

4. The better way, first try to display simple program like “Hello world” on the DE2 development board.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎06-13-2018

Hello there, this code did not work, so I created a new 4-bit counter and text environment for it but I can not display the signal on 4 7- segment displays ????

architecture beh of johnson_counter is
signal opt: std_logic_vector( 3 downto 0 );
begin
process( clk, rst )
begin
if( rst = '1' ) then
     opt <= "0000";
elsif( rising_edge( clk ) ) then
opt <=( not opt( 0 ) ) & opt( 3 downto 1 );
end if;
end process;
op <= opt;
end beh;
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity johnson_counter_tb is
end johnson_counter_tb;
architecture Behavioral of johnson_counter_tb is
component johnson_counter is
port( clk: in std_logic;
rst: in std_logic;
op: out std_logic_vector( 3 downto 0 ) );
end component;
signal clk_tb, rst_tb: std_logic:= '1';
signal op_tb: std_logic_vector( 3 downto 0 );
constant clk_period: time:= 10 ns;
begin
DUT: johnson_counter port map( clk_tb, rst_tb, op_tb );
clk_process: process
begin
clk_tb <= not( clk_tb );
wait for clk_period / 2;
end process;
main_process: process
begin
wait for 10 ns;
rst_tb <= '0';
wait for 100 ns;
end process;
end Behavioral;

Altera_Forum · ‎06-15-2018

What is the result of your testbench? What did you expect and what did you get?

Altera_Forum · ‎06-15-2018

In my task, it's all about making any Jonson counter. Which will be displayed on 4 seven segment LED displays. The status of the display changes every 1s. And develop a text environment.

Altera_Forum · ‎06-15-2018

If I'm not mistaken the last code you provided, if connected to 4 leds, will turn each led on one by one, until all 4 are on, and then turn them off. If you intended to use those signals on the common pins of the 7 segment displays it will not work as expected because you will have often several display activated at the same time. The first code you provided will be better suited for this.

You have the code to control the common pin, and the code to translate from a binary value to 7 segments. Now you need to implement registers with BCD counters and connect everything together.

Altera_Forum · ‎06-15-2018

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Counter2_VHDL is port( Clock_enable_B: in std_logic; Clock: in std_logic; Reset: in std_logic; Output: out std_logic_vector(0 to 3)); end Counter2_VHDL; architecture Behavioral of Counter2_VHDL is signal temp: std_logic_vector(0 to 3); begin process(Clock,Reset) begin if Reset='1' then temp <= "0000"; elsif(rising_edge(Clock)) then if Clock_enable_B='0' then if temp="1001" then temp<="0000"; else temp <= temp + 1; end if; end if; end if; end process; Output <= temp; end Behavioral;

Altera_Forum · ‎06-19-2018

Hi,

Have you resolved the issue which was you facing? What are you trying to do with this code in previous post?

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎07-02-2018

I need a course of time or some simulation this task the code is working correctly I'm sure but I do not have access to the program anymore.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity seven_segment_display_VHDL is
    Port ( clock_100Mhz : in STD_LOGIC;-- 100Mhz clock on Basys 3 FPGA board
           reset : in STD_LOGIC; -- reset
           Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals
           LED_out : out STD_LOGIC_VECTOR (6 downto 0));-- Cathode patterns of 7-segment display
end seven_segment_display_VHDL;
architecture Behavioral of seven_segment_display_VHDL is
signal one_second_counter: STD_LOGIC_VECTOR (27 downto 0);
-- counter for generating 1-second clock enable
signal one_second_enable: std_logic;
-- one second enable for counting numbers
signal displayed_number: STD_LOGIC_VECTOR (15 downto 0);
-- counting decimal number to be displayed on 4-digit 7-segment display
signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0);
signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0);
-- creating 10.5ms refresh period
signal LED_activating_counter: std_logic_vector(1 downto 0);
-- the other 2-bit for creating 4 LED-activating signals
-- count         0    ->  1  ->  2  ->  3
-- activates    LED1    LED2   LED3   LED4
-- and repeat
begin
-- VHDL code for BCD to 7-segment decoder
-- Cathode patterns of the 7-segment LED display 
process(LED_BCD)
begin
    case LED_BCD is
    when "0000" => LED_out <= "0000001"; -- "0"     
    when "0001" => LED_out <= "1001111"; -- "1" 
    when "0010" => LED_out <= "0010010"; -- "2" 
    when "0011" => LED_out <= "0000110"; -- "3" 
    when "0100" => LED_out <= "1001100"; -- "4" 
    when "0101" => LED_out <= "0100100"; -- "5" 
    when "0110" => LED_out <= "0100000"; -- "6" 
    when "0111" => LED_out <= "0001111"; -- "7" 
    when "1000" => LED_out <= "0000000"; -- "8"     
    when "1001" => LED_out <= "0000100"; -- "9" 
    when "1010" => LED_out <= "0000010"; -- a
    when "1011" => LED_out <= "1100000"; -- b
    when "1100" => LED_out <= "0110001"; -- C
    when "1101" => LED_out <= "1000010"; -- d
    when "1110" => LED_out <= "0110000"; -- E
    when "1111" => LED_out <= "0111000"; -- F
    end case;
end process;
-- 7-segment display controller
-- generate refresh period of 10.5ms
process(clock_100Mhz,reset)
begin 
    if(reset='1') then
        refresh_counter <= (others => '0');
    elsif(rising_edge(clock_100Mhz)) then
        refresh_counter <= refresh_counter + 1;
    end if;
end process;
 LED_activating_counter <= refresh_counter(19 downto 18);
-- 4-to-1 MUX to generate anode activating signals for 4 LEDs 
process(LED_activating_counter)
begin
    case LED_activating_counter is
    when "00" =>
        Anode_Activate <= "0111"; 
        -- activate LED1 and Deactivate LED2, LED3, LED4
        LED_BCD <= displayed_number(15 downto 12);
        -- the first hex digit of the 16-bit number
    when "01" =>
        Anode_Activate <= "1011"; 
        -- activate LED2 and Deactivate LED1, LED3, LED4
        LED_BCD <= displayed_number(11 downto 8);
        -- the second hex digit of the 16-bit number
    when "10" =>
        Anode_Activate <= "1101"; 
        -- activate LED3 and Deactivate LED2, LED1, LED4
        LED_BCD <= displayed_number(7 downto 4);
        -- the third hex digit of the 16-bit number
    when "11" =>
        Anode_Activate <= "1110"; 
        -- activate LED4 and Deactivate LED2, LED3, LED1
        LED_BCD <= displayed_number(3 downto 0);
        -- the fourth hex digit of the 16-bit number    
    end case;
end process;
-- Counting the number to be displayed on 4-digit 7-segment Display 
-- on Basys 3 FPGA board
process(clock_100Mhz, reset)
begin
        if(reset='1') then
            one_second_counter <= (others => '0');
        elsif(rising_edge(clock_100Mhz)) then
            if(one_second_counter>=x"5F5E0FF") then
                one_second_counter <= (others => '0');
            else
                one_second_counter <= one_second_counter + "0000001";
            end if;
        end if;
end process;
one_second_enable <= '1' when one_second_counter=x"5F5E0FF" else '0';
process(clock_100Mhz, reset)
begin
        if(reset='1') then
            displayed_number <= (others => '0');
        elsif(rising_edge(clock_100Mhz)) then
             if(one_second_enable='1') then
                displayed_number <= displayed_number + x"0001";
             end if;
        end if;
end process;
end Behavioral;