Virtual pins and their input delays [TimeQuest]

[Altera_Forum]

Hello all, 

 Developing only one part of an FPGA architecture, I constrained most of my design's pins as virtual in the Assignment Editor (both inputs and outputs, except some inputs, including clocks ofc). While I successfully constrained my Clocks and non-virtual inputs in my SDC, I am left with a massive number of unconstrained ports in TimeQuest. I am unsure if that situation is normal, thus I tried constraining with 0 input delay, provoking confusion to TimeQuest that considers that none of my inputs are multicycle paths (Which I could manually change).  All my virtual inputs will, in the future, be registers inside the FPGA, and I have no idea if I am supposed to simply ignore the errors I've had in TimeQuest for now, or if I am to constrain my virtual pins according to typical Tsu and Th of my FPGA (Cyclone III); or else:confused:?  I hope some of you may help me with that matter, as I was not able to find any answer across the Internet. Thanks in advance, Nicolas.

[Altera_Forum]

--- Quote Start ---  Hello all,  Developing only one part of an FPGA architecture, I constrained most of my design's pins as virtual in the Assignment Editor (both inputs and outputs, except some inputs, including clocks ofc). While I successfully constrained my Clocks and non-virtual inputs in my SDC, I am left with a massive number of unconstrained ports in TimeQuest. I am unsure if that situation is normal, thus I tried constraining with 0 input delay, provoking confusion to TimeQuest that considers that none of my inputs are multicycle paths (Which I could manually change).  All my virtual inputs will, in the future, be registers inside the FPGA, and I have no idea if I am supposed to simply ignore the errors I've had in TimeQuest for now, or if I am to constrain my virtual pins according to typical Tsu and Th of my FPGA (Cyclone III); or else:confused:?  I hope some of you may help me with that matter, as I was not able to find any answer across the Internet. Thanks in advance, Nicolas.  --- Quote End ---    I understand you are designing module level to be handed then for integration. In this case don't worry about io and just accept the warning of undefined io constraints.  your main issue is passing fmax within your module from your input registers to your output registers. The io paths outside are irrelevant. alternatively if you wish you can add false path on your io