Waveform- Forcing Unknown(X)

[Altera_Forum]

Hello , i have a problem about the waveform simulation. I have design the mic1 processor and i want to add A[32](bus line) + B[32] ((bus line)=C[32](bus line). For example A=200 and B=0. When i run this execution separately in the datapath_block and ALU_block i take correct results in the C bus. But when i run the DATAPATH_UNIT( a block which contains the combination of the previous two) with the whole processor also ( main memory, control unit ) , then i take forcing unknown in the C[0] signal. Any ideas whats going wrong? I have simulate all the schematics individually and they are all working fine. 

Regards,   Kostas

[Altera_Forum]

The simulator typically generates 'x' if you haven't initialised a register/signal that forms part of the combinatorial input logic. So, I'd suggest you haven't connected it up as you think you have or you haven't initialised either 'A' and/or 'B' as you refer to them. 

 Cheers, Alex

[Altera_Forum]

Finally, i set a value for the fmax in the classic timing analyzer wizard and now is working fine. Now the next problem is, when it has to read some data from an address ( i use the altsyncram block) it doesn't makes it right. For example i want to read the value 5 from the address 200. In the mif file i have type the 5 in the '200 space'. I have also put pins in the altsyncram for the address and the data and in the waveform during the clock cycle which the read signal is 1, the result of the address is 200 when the clock goes from0 to 1, but the data doesn't change. May i have to set a different value in fmax or set a higher period?

[Altera_Forum]

'altsyncram' blocks typically have registers on their input signals and optionally on it's output signals. So, the value on 'q' won't be valid for up to 2 clock cycles after the address is presented. 

 Could this explain what you're seeing?  Cheers, Alex  PS. As you've opened this on another thread I suggest you don't continue posting on this one :)