What does this error message mean?

Altera_Forum · ‎10-19-2010

What does this error message mean? It occurs when I try to do a blank check on the plds in my pcb (or any other JTAG action on the board).

Internal Error: Sub-system: PGME, File: /quartus/pgm/pgme/pgme_algorithm.cpp, Line: 1265

Illegal tap position

Stack Trace:

0xe666: PGME_JTAG_CHAIN::read_dr_loop + 0x1bf6 (pgm_pgme)

0x3129b: pgme_check_for_y1_device + 0x124b (pgm_pgme)

0x990f: PGME_JTAG_CHAIN::set_padding + 0x40f (pgm_pgme)

End-trace

Quartus II Version 9.1 Build 304 01/25/2010 SJ Web Edition

Service Pack Installed: 1

I presume I have a pcb problem, but it doesn't help that every time I try JTAG then QII crashes.

Altera_Forum · ‎10-19-2010

Further experiments show that a different pcb type with the same JTAG pattern (non-altera CPU, 4 * MAXII) runs ok (ie doesn't crash, but does fail blank check because they aren't blank).

However if a make a programming *.cdf with the CPU and only 3 * MAXII then it crashes in the same way.

Hmmm...

Altera_Forum · ‎10-26-2010

If anyone is interested, it turned out to be a solder splash between TCK and TDO on the final pld in the chain.

I still don't see why this should cause Quartus to crash. IMO it should just display an error message but keep running.