How does FPGA's IP core data format be arranged?
According to the instructions, when I send them, I arrange them in this way.
jesd204b_tx_link_data[127:0] = {I0,I1,I2,I3,I4,I5,I6,I7}
jesd204b_tx_link_data[127:0] = {Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7}
But this data maping is wrong.
I configure LMFS is 8212
Just like in the picture, is there an example of 8lane?
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Hi!
We have faced the same problem with LMFS = 8212.
DAC is different (AD9161), but it seems that the problem is with wrong mapping in Arria10 side.
Would you mind helping us with this mapping???
We sent complex sine wave, but the image was very far from expected.
The right mapping for [AD9161 LMFS=8212 + JESD204B Intel FPGA IP] is
