What's the Altera Equivalent to the Xilinx STARTUP Primitive GSR/GlobalSetReset?

Altera_Forum · ‎09-06-2016

Here's an example of what it looks like for Xilinx:

// Instantiating STARTUP symbol

STARTUP U1 (.GSR(global_reset));

always @(posedge clk or posedge global_reset) begin

if (global_reset) begin

dff <= 1'b0;

end

else begin

dff <= xyz;

end

Ok...Altera how to do it without needing a clock and initial conditions to create a global reset?

The reason why I ask is because I have a QSYS with an HPS core that is outputing a clock from a pll and the top-level FPGA doesn't have a Clock or reset pin that is accessable to the FPGA logic...

Altera_Forum · ‎09-07-2016

To answer your main question - there is no Altera equivalent to the GSR primitive.

You should be able to route the clock and a reset signal from the HPS to the FPGA fabric directly. What problem are you having? Export the signals in Qsys and then in the top-level HDL wrapper (I assume) that instantiates your Qsys module and your FPGA module just wire the clock and reset from the Qsys module to the FPGA module.