Which clock should I use for JTAG UART Module?

[Altera_Forum]

Hello! 

I have Qsys system containing NIOS II/e, SDRAM Controller, JTAG UART , SysID and Some PIO. I am using DE1 Altera board with cyclone II on it  Right now I am trying to speed the system up to 166 MHz (max. SDRAM speed). My question:  What CLK should go to JTAG UART, SysID and PIO's? Same as for NIOS? Or is 166Mhz too fast for them? I have tried to use 166 MHz for every component, but my NIOS doesn't react (till ca. 120 MHz everything works fine). The Datasheet says, I can run NIOSII up to 195 MHz on Cyclone II, so 120 MHz should be the limit, I hope... Can anyone help me?=)

[Altera_Forum]

You can connect them to any clock, but don't forget to use Avalon-MM clock crossing bridge.

[Altera_Forum]

I'd say connect the same clock to JTAG UART, SysID and PIO as the NIOS clock. If NIOS can meet the timing, those should be able to too. I don't think you need clock crossing bridge. JTAG UART component itself handles clock crossing to JTAG clock within.

[Altera_Forum]

Avalon-MM clock crossing bridge is not needed, but helps to achieve better timing results.

[Altera_Forum]

--- Quote Start ---  Avalon-MM clock crossing bridge is not needed, but helps to achieve better timing results.  --- Quote End ---    How does it? I read the description of this bridge. It throws in a FIFO to handle data exchange between two clock domains. Since FIFO is implemented in ram, which has fixed location on the device. It creates additional location constraint to placement. Hence, it can actually limit timing result. Does qsys do anything clever if it detects that two clocks at the two ends of the bridge are the same? It seems that Avalon-MM pipeline bridge is designed to improving timing by trading off some additional latency of transaction.

[Altera_Forum]

The Avalon-MM clock crossing bridge will mostly help achieve better performance. I'm not sure about it's consequences on signal timing. 

Is the clock crossing bridge has FIFOs it can pipeline several requests between the two domains, resulting in better performance with masters that can do pipelining (mostly DMAs, and the CPU if it has caches). If you connect two components from different clock domains without the clock crossing bridge, QSys will generate much simpler clock crossing logic that will work but that can only handle one transaction at a time.