- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
Hello, can anyone tell me if ModelSim Altera Edition supports SystemVerilog Assertions? IF not should I get ModelSim PE, DE, or SE?
thanks, joe링크가 복사됨
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
I got this from Altera's web site:
ModelSim-Altera Starter Edition software is the same as ModelSim-Altera Edition software except for two areas. ModelSim-Altera Starter Edition’s simulation performance is lower than ModelSim-Altera Edition and has a line limit of 10,000 executable lines compared to the unlimited number of lines allowed in the ModelSim-Altera Edition. I guess that's the answer right there. Sorry for the nu-necessary post. joe- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
Can anyone tell me how much I will need to spend to get a simulator that supports SystemVerilog for Verification?
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
Only Modelsim DE supports proper SystemVerilog assertions. The problem is that many proprietary "assertion based verification" tools and verilog add-ons have been proposed by HDL vendors (i.e. PSL, sugar... etc). And now finally after many years they finally decided to standardize them and introduce them to the standard language, so you need to give modelsim some time to implement them. Not good for us SystemVerilog users I know :(
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
I just started to compile assertions with Modelsim DE. Has anyone tried using Assertions in DE? I am wondering what kind of performance can I expect.
