Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15322 Discussions

Why do all registers return 0 when simulating the dual boot IP core in a MAX10 device.

BAdam1
Beginner
1,663 Views

I am trying to verify the functionality of the dual boot IP core in a MAX10 device. I issue a write to set bit 3 of offset 2 (See page 60 of ug_m10_config.pdf) The strange thing about this Write is that the response from the Avalon Packet interface indicates a successful write of 3 bytes not 4 bytes. I then Read offset 7 and it reads 0. I then write a '1' to offset 1 bit 1 to change the CONFIG_SEL value in the input register. I then check offset 3 to make sure that the core is not Busy. After that, I write to bit 3 of offset 2 again to trigger a read of the input register. When I read offset 7 again, it remains unchanged. It is still 0. I have tried Big Endian and Little Endian. Is there a problem simulating this core? Does it only work on an actual device?

0 Kudos
4 Replies
SAR
Novice
132 Views

Hi,

 

Can you elaborate more on your design and steps involved in simulation?

Try simulation for example in link below.

https://fpgacloud.intel.com/devstore/platform/17.1std.1/Standard/dualboot-design-example/

BAdam1
Beginner
132 Views
I am trying to verify the functionality of the dual boot IP core in a MAX10 device.  I issue a write to set bit 3 of offset 2 (See page 60 of ug_m10_config.pdf)  The strange thing about this Write is that the response from the Avalon Packet interface indicates a successful write of 3 bytes not 4 bytes.  I then Read offset 7 and it reads 0.  I then write a '1' to offset 1 bit 1 to change the CONFIG_SEL value in the input register.  I then check offset 3 to make sure that the core is not Busy.  After that, I write to bit 3 of offset 2 again to trigger a read of the input register.  When I read offset 7 again, it remains unchanged.  It is still 0.  I have tried Big Endian and Little Endian.  Is there a problem simulating this core?  Does it only work on an actual device? Bill Adams
BAdam1
Beginner
132 Views
I also have the On-Chip Flash Intel FPGA IP core in this design.  I am able to access the Control and Status registers with no problem.  I have been able to simulate, read, write and erase. Bill Adams
ShafiqY_Intel
Employee
132 Views

Hi,

 

Here are you answer:

 

I issue a write to set bit 3 of offset 2 (See page 60 of ug_m10_config.pdf)The strange thing about this Write is that the response from the Avalon Packet interface indicates a successful write of 3 bytes not 4 bytes. I then Read offset 7 and it reads 0. 

You need to trigger CONFIG_SEL_OVERWRITE (offset 1, bit 0) and CONFIG_SEL (offset 1, bit 1) if you want to make a change to the CONFIG_SEL (offset 7, bit 1) value.

                                                                                                                                                                                       

I then write a '1' to offset 1 bit 1 to change the CONFIG_SEL value in the input register. …….. When I read offset 7 again, it remains unchanged. It is still 0. 

If you want to change the CONFIG_SEL (offset 7, bit 1) value, you need to write 1 to CONFIG_SEL_OVERWRITE.

 

For example, if you want to load from image 1, you need to write a ‘1’ to bit 0(offset 1) and bit 1(offset 1). You should write b’211 to offset 1.

Then, if you want to read back the value, you need to write a ‘1’ to bit 3 (offset 2). You should write b’41000 to offset 2.

As the result, when you read offset 7, it will show b’211. b’211 indicate  CONFIG_SEL_OVERWRITE and CONFIG_SEL triggers.

 

Thank you.😉

Reply