VHDL external names are where we use the << and >> symbols to declare an alias to a signal in another level of hierarchy in the design. They are often used in testbench code.
It seems that this feature is not allowed in Intel Quartus Prime for synthesis. I get this error when I declare a hierarchical signal:
Error (10500): VHDL syntax error at LED.vhd(16) near text "<"; expecting an identifier, or a string literal
Why is this feature not supported for synthesis?
I am sorry for missing out the information. I think your reply is not reflected in the forum replies (see below)
Have you tried to compile in the Pro edition? The Standard edition has limited language support for VHDL-2008. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pd....
I do not have license for the pro edition. It seems that this feature in the language is intended for testbenches and not intended to be supported in synthesis.
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