Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Why doesn't the output data toggle when running a gate-level simulation (.sdf)?

Altera_Forum
Honored Contributor II
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In order to view output data that toggles at a high frequency in a third-party simulation tool, enable the transport switches in the simulation tool.  

 

The following switches must be enabled: 

 

+transport_int_delays  

+transport_path_delays  

+pulse_r/0  

+pulse_e/0  

For example, invoke VCS with the follow command: 

 

vcs <my_test_bench.v> <my_design_file.v> +transport_int_delays +transport_path_delays +pulse_r/0 +pulse_e/0 

 

Below is a description of each switch: 

 

+transport_int_delays: Allows propagation of all pulses that are narrower than the SDF INTERCONNECT delay.  

+transport_path_delays: Allows propagation of all pulses that are narrower that the inter-module path delay.  

+pulse_e/<number>: Rejects (flags as error and drives X) any pulse with a width is less than or equal to the specified percentage of the module path delay . The <number> argument is a percentage in the range of 0 to 100.  

+pulse_r/<number>: Rejects any pulse with a width less than the specified percentage of the inter-module path delay. The <number> argument is a percentage in the range of 0 to 100. 

The above transport switches are not enabled by default. For further information on these switches, refer to your simulation tool's user manual.
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Altera_Forum
Honored Contributor II
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Along the same lines, if you are performing gate level timing simulations with Cadence NCsim simulator, the equivalent switches to transport cell and interconnect delays are: 

-PULSE_R and -PULSE_INT_R 

 

e.g. 

ncelab work.<my design> -TIMESCALE 1ps/1ps -PULSE_R 0 -PULSE_INT_R
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