You really need to take a look at your process sensitivity list - there is no way that this would be synthesizable (and may be the cause of your simulation issues). From the looks of your code, I'd say the only thing that should be in your sensitivity list is clk. For this kind of interface, you don't really want to use sclk as a true clock, use it as a signal to tell you when to sample/control the rest of the SPI interface.
Hi, also second process has no edge, so it is async, sensitivity list has no sense how is used as noted from AndyN.
Reset if used on async has no sense on clock event:
when INIT=> if cs_n='0' and reset_n ='1' then state <= DF; else state <= INIT; end if;
second process has no event so it is Async.
- process(state, sclk, din, cs_n, clk) is
- case state is
- when INIT =>
- -- new_data <='0';
- counter <= 0;
- t_bus <= "00100000000000000";
- -- regnr<="00";
- -- regwrite_n<='1';
- -- regcontent<=(others=> '0');
try read this book, you can find an example of SPI and how to code in VHDL.
Hi, clean up code and learn VHDL event.
at second glance, many issue are on your code, don't use elsif with event:
if reset_n ='0' then .. reset actions else if rising_edge(clk) then .. clock event end if; -- clock event end if; -- reset
State is a signal assigned from clock on first process, can be ok but if you wish state be an event remove conflicting rising_edge on midst of code.
First process is event driven from rising edge of same clk.
On SPI need use both rising and falling clock event, derive them from an edge detector or code the right way, receiving on one edge transmitting on the other edge.
I assume this is a slave SPI, so your clock is slow (5MHz) and you own a fast clock too.
Sample SPI on a two/three stage shift register on fast clock then check for rising falling sequence 001 110.
Drive all logic from fast clock using edge detector as clock enable.
Second process as case assignment instead of combinatorial when else need have just case in sensitivity list.
try post cleaned code.
In first process you are sampling cs by a faster clock. This faster clock has nothing to do with SCLK of SPi.
Am I right? So you cannot count bit from clk, you need do instead from SCLK edges.
If process is run from clk the only alternative is to sample slow sclk and derive edges to count bit and shift in/out data. Or add another process where clock is SCLK.
Is this an SPI or just some way of lab with off topic name?
Main clock (clk) which is faster is responsible for this SPI slave's IO ports and internal state actions on rising edge synchronization. Sclk is to fetch data from Serial data in port (din) within 17cycles on falling edge. you can see it as a mosi.
Dear sir, erasing code from first post is nothing good.
Befrore to teach someone also the weackest basic, one need fully grasp subject. About HDL and FPGA you never can reach this level than working on for long long time. And long long time in Very complex language and topic as VHDL/FPGA is a life challenge. About this since 40 Yr ago on Programmable devices I cannot affirm know VHDL or FPGA domain in every shades.
About your code I feel I have nothing to see than remember was a mess as all of us can sometimes do when we are at initial stage of learning curve.
About clock your description is far away from understandable as was your coding. Nothing bad on ask, we are proud on spare time help to grew up to engage professional grade from error.
What instead as teacher and old professional (someone correct me if I am wrong) I read from wording is a preloaded arrogance. Is spread areound all world on Young pupils on the idea they can do everything just asking some google or forum.
This is a worst perception and denote low capacity of learn by theory respecting who is n front of them also if hidden behind some screens.
As old teacher I can also learn from my pupils, I learn how to guide them to great professional career. I try learn how to avoid error from technology. Some times I fails in front of them hiding on small gaming screen. Sorry but this sound me as one of that cases.