Why the task cannot be synthesisd?

[Altera_Forum]

I just try to use a task to improve the programming efficiency. The code is as following: 

  task TwoNumberMin; input [RamWidth-1:0] a,b; input clk; output [RamWidth-1:0] min;  always @(posedge clk) begin if (a>b) min<=b; else min<=a; end   endtask   TwoNumberMin(.a(noiseCeil),.b(LPF_out_1d),.clk(clk),.min(modifiedValue));  But there is always error "Error (10170): Verilog HDL syntax error near text "always"; expecting ";"  I can't understand this message. The commands inside the task are all synthesisd, but why my code can not be synthesisd?  Please help me, thanks!

[Altera_Forum]

Try putting a 'begin' and 'end' around the always statement. 

Although I don't understand why the language requires this as you only have a single statement.  Regards, ++Simon

[Altera_Forum]

Hello, Simon. Thanks for your reply. But I don't understand where I should put "begin" and "end"? Because I already have begin and end for my always. Could you please modify my code and paste in your reply? 

 Thanks very much!

[Altera_Forum]

Try: 

 task TwoNumberMin; input [RamWidth-1:0] a,b; input clk; output [RamWidth-1:0] min;  begin  always @(posedge clk) begin if (a>b) min<=b; else min<=a; end   end  endtask    I find if there is a problem it is quickest to use a search engine for the construct you are having syntax problems with. In this case: "verilog task" brings up lots of helpful answers.  It would be nice if the error messages from the tools were more helpful too! (Often the error is in the previous line - not the line that gives the error message.)  ++Simon

[Altera_Forum]

Hello Simon, Thanks for your code. I tried it in my program but it still doesn't work, and Quartus II gave the same error.

[Altera_Forum]

I should have taken my own advice! From "Summary of Verilog Syntax" pdf 

 "6. Tasks & Functions Tasks and functions in Verilog closely resemble the procedures and functions in programming languages. Both tasks and functions are defined locally in the module in which the tasks and functions will be invoked. No initial or always statement may be defined within either tasks or functions."  It would also be nice if the compiler told us we were not being clever!  For this example a function would probably be the way to go.  ++Simon

[Altera_Forum]

Yes, Simon. I think you are right!

[Altera_Forum]

And the right code: 

 module Tasktest(A,B,clk,C); input [5:0] A,B; input clk; output [5:0] C;  always @ (posedge clk) begin  Min(A,B,clk,C); end  task Min; input [5:0] a,b; input clk; output reg [5:0] min; //  begin //always @ (posedge clk); if (a>b) min<=b; else min<=a;  end  endtask    endmodule

[Altera_Forum]

This is a Verilog language rule that has nothing to do with synthesis. 

 Tasks and functions may only contain variable declarations and procedural statements. always and initial are not procedural statements, they are process declarations.   You could replace the always inside your task with the procedural looping statement forever for simulation, but most synthesis tools do not allow unbounded procedural loops.

[Altera_Forum]

Thanks very much&#65281;