Why this last unconstrained path?

Altera_Forum · ‎08-26-2009

I am fairly new to TimeQuest, finishing off my first project using it. I almost have a clean report, except for a last unconstrained path which I don't know what to do with.

I have a 50 MHz external clock, which is used for part of the design. A PLL generates a 33 MHz clock which is used for the 2nd part. The 33 MHz clock is also fed out on a port (renamed Clk33_Out). This port is constrained like this:

set_max_delay -from [get_ports clk_50] -to [get_ports Clk33_Out] 12.

TimeQuest reports a partially constrained port under hold analysis, with an unconstrained path:

from PLL_inst|Pll_Clk[0] (that is the 50MHz clk)

to Clk33_Out

from Clk_50.

The setup analysis is clean.

The Unconstrained paths > Clock Status Summary shows CLk33 as generated and constrained.

What am I missing?

Altera_Forum · ‎08-26-2009

Clock sources (includes generated clocks such as PLL clocks) are startpoints of timing paths. Timing exceptions (e.g., set_max_delay) cannot be applied "across" a startpoint.

The set_max_delay is from the input clock port to the output clock port, which passes across the PLL clock. This means your set_max_delay exception was ignored. If you call report_timing with the exact same -from/-to arguments and you should see zero paths reported. You can also use report_exceptions to verify your exceptions (Quartus II 9.0 and newer).

Instead try simply (dropping the -from):

set_max_delay -to [get_ports Clk33_Out] 12

or:

set_max_delay -from [get_clocks name_of_pll_clk] -to [get_ports Clk33_Out] 12

You'll also need a set_min_delay to satisfy hold timing.

Altera_Forum · ‎08-26-2009

Very clear, now that you said it, Gopher. Problem solved. Big thanks.