Writing values into memory and reading those values. Timing Issue!!!

[Altera_Forum]

Hi,  

 I am trying to design a memory (logic [7:0] memory [0:31]) in system verilog. First I write 0s into all the address of my memory, then I read one by one. After writing 0 into the address memory[31], i start reading from memory[0]. But i am getting x. I think there is some race condition or setup time violation. Please help me with this. Dont get confused with the system verilog constructs. I just want to know how to fix the timing issue here.  Here is my code:   module mem_test(input logic clk, output logic read, write, output logic [4:0] addr, output logic [7:0] data_in, input logic [7:0] data_out);timeunit 1ns;timeprecision 1ps;bit debug=1'b0;//logic [7:0] rdata_out;task write_mem(input logic [4:0] waddr, input logic [7:0] wdata_in, input logic debug); @(negedge clk) begin addr <= waddr; data_in <= wdata_in; write <= 1'b1; read <= 1'b0; end unique if(debug) begin $display("addr=%b, data_in=%b", waddr, wdata_in); endendtasktask read_mem(input logic [4:0] raddr, input logic debug); @(negedge clk) begin # 10 addr <= raddr; read <= 1'b1; write <= 1'b0; //#2 rdata_out <= data_out; end //rdata_out <= data_out; unique if(debug) begin $display("addr=%b, data_out=%b", raddr, data_out); endendtask initial begin//genvar i, j, k, l;for(int i=0;i<=31;i++) begin write_mem(i,8'd0,1'd1);endbegin for(int j=0;j<=31;j++) begin read_mem(j,1'd1); endendfor(int k=0;k<=31;k++) begin write_mem(k,k,1'd1);endbegin for(int l=0;l<=31;l++) begin read_mem(l,1'd1); endend#500 $finish;endendmodule

[Altera_Forum]

Can you repost the code with some carrige returns? And maybe code tags?

[Altera_Forum]

Sorry about it. I am new to this forum. Here You go !!! 

  module mem_test(input logic clk, output logic read, write, output logic addr, output logic data_in, input logic data_out); timeunit 1ns; timeprecision 1ps; bit debug=1'b0; //logic rdata_out; task write_mem(input logic waddr, input logic wdata_in, input logic debug); @(negedge clk) begin addr <= waddr; data_in <= wdata_in; write <= 1'b1; read <= 1'b0; end unique if(debug) begin $display("addr=%b, data_in=%b", waddr, wdata_in); end endtask task read_mem(input logic raddr, input logic debug); @(negedge clk) begin # 10 addr <= raddr; read <= 1'b1; write <= 1'b0; //#2 rdata_out <= data_out; end //rdata_out <= data_out; unique if(debug) begin $display("addr=%b, data_out=%b", raddr, data_out); end endtask initial begin //genvar i, j, k, l; for(int i=0;i<=31;i++) begin write_mem(i,8'd0,1'd1); end begin for(int j=0;j<=31;j++) begin read_mem(j,1'd1); end end for(int k=0;k<=31;k++) begin write_mem(k,k,1'd1); end begin for(int l=0;l<=31;l++) begin read_mem(l,1'd1); end end # 500 $finish; end endmodule

[Altera_Forum]

When I re-post it again, I am not able to see it !!! Should i create a new post ?

[Altera_Forum]

This looks like a software attempt at some hardware. I don't see an array to store any data?

[Altera_Forum]

--- Quote Start ---  This looks like a software attempt at some hardware. I don't see an array to store any data?  --- Quote End ---    This is the test bench. I have declared the memory in the design. From the test bench i am giving only the address, data, and other necessary signals.

[Altera_Forum]

And how is the mem defined? What is the memory code? 

Why do you delay the read address on a read task?

[Altera_Forum]

--- Quote Start ---  And how is the mem defined? What is the memory code? Why do you delay the read address on a read task?  --- Quote End ---    Memory is defined as logic [7:0] memory [0:31] Please find the entire code below. The memory module and test bench are instantiated in the top module.   ****************** TOP MODULE ****************** module top;// SYSTEMVERILOG: timeunit and timeprecision specification timeunit 1ns; timeprecision 1ns; // SYSTEMVERILOG: logic and bit data types bit clk; wire read; wire write; wire addr; wire data_out; // data_from_mem wire data_in; // data_to_mem // SYSTEMVERILOG:: implicit .* port connections mem_test test (.*); // SYSTEMVERILOG:: implicit .name port connections mem memory ( .clk, .read, .write, .addr, .data_in, .data_out ); always# 5 clk = ~clk; endmodule      *********************** MEMORY MODULE *********************** module mem ( input clk, input read, input write, input logic addr , input logic data_in , output logic data_out ); // SYSTEMVERILOG: timeunit and timeprecision specification timeunit 1ns; timeprecision 1ns; // SYSTEMVERILOG: logic data type logic memory ; always @(posedge clk) if (write && !read) // SYSTEMVERILOG: time literals memory <= data_in; // SYSTEMVERILOG: always_ff and iff event control always_ff @(posedge clk iff ((read == '1)&&(write == '0)) ) data_out <= memory; endmodule  Below is the output. I am writing "zero" in all the addresses and reading. You willbe seeing "x" once i start the reading process. That's the issue i am trying to fix.   **************************** OUTPUT ****************************** addr=00000, data_in=00000000 addr=00001, data_in=00000000 addr=00010, data_in=00000000 addr=00011, data_in=00000000 addr=00100, data_in=00000000 addr=00101, data_in=00000000 addr=00110, data_in=00000000 addr=00111, data_in=00000000 addr=01000, data_in=00000000 addr=01001, data_in=00000000 addr=01010, data_in=00000000 addr=01011, data_in=00000000 addr=01100, data_in=00000000 addr=01101, data_in=00000000 addr=01110, data_in=00000000 addr=01111, data_in=00000000 addr=10000, data_in=00000000 addr=10001, data_in=00000000 addr=10010, data_in=00000000 addr=10011, data_in=00000000 addr=10100, data_in=00000000 addr=10101, data_in=00000000 addr=10110, data_in=00000000 addr=10111, data_in=00000000 addr=11000, data_in=00000000 addr=11001, data_in=00000000 addr=11010, data_in=00000000 addr=11011, data_in=00000000 addr=11100, data_in=00000000 addr=11101, data_in=00000000 addr=11110, data_in=00000000 addr=11111, data_in=00000000 addr=00000, data_out=xxxxxxxx addr=00001, data_out=00000000 addr=00010, data_out=00000000

[Altera_Forum]

Can anyone help me with this ?  

Thanks