Wrong node type for node in vector source file (vhdl file). Jk flop

[Altera_Forum]

Design node type is of Output type but in signal in vector file is bidirectional. (QUARTUS II) 

 My code for a JK flip flop compiles correctly but the problem I am having is that when I try to run simulation, an error occurs. I've been troubleshooting/debugging for 2 days now with no luck. Any advice?  entity jkflop is port (  j,k,clk,pre,clr: in bit;  q, qn: out bit); end jkflop; architecture behavior of jkflop is begin  PROCESS(clk,pre,clr)  variable q1: bit;  begin  if pre = '0' then  q1:= '1';  elsif clr = '0' then  q1:= '0';  elsif (clk 'event AND clk = '0') then  if (j = '0' AND k = '0') then  q1:= q1;  elsif (j = '1' AND k = '0') then  q1:= '1';  elsif (j = ''0' AND k = '1') then  q1:= '0';  else  q1:= NOT q1;  END if;  END if;  q<= q1;  qn<= NOT q1;  END PROCESS; END behavior;

[Altera_Forum]

My Q and QN waveforms do not simulate correctly.

[Altera_Forum]

What error is occurring

[Altera_Forum]

--- Quote Start ---  What error is occurring  --- Quote End ---    Warning: Wrong node type for node "q" in vector source file. Design node is of type Output, but signal in vector source file is of type Bidir. Error: Can't simulate mismatched node types. Warning: Wrong node type for node "qn" in vector source file. Design node is of type Output, but signal in vector source file is of type Bidir. Error: Can't simulate mismatched node types.  Any time I run my simulation, I receive those warning. My outputs q and qn show unknown values, my simulated results page takes my end time from 1us to 10us, and my inputs have all changed per that results page as well. I don't think half of that stuff is an issue, except for the node type problem....that is what I am trying to solve.

[Altera_Forum]

Your vwf isnt setup correctly. I highly suggest you write your own testbench rather than try and use a VWF file for testing.