Zero Packed Or Unpacked Array Dimensions Problems

[Altera_Forum]

Hi bros. I want to implement a circuit that run like this: 

- If reset = 0, the output data = 12'b0; - If not, the output data = a vector in the ROM. And this is my code (I apologize for its length, but you can ignore what is in the concatenation operator)  module ROM_sin  (  input clk, rst,  input [10:0] addr,  output reg [11:0] data  );  reg [10:0] temp; integer i; reg [11:0] RAM_2048_12BIT [2047:0];  assign MY_ROM = {12'b000000000000, 12'b000000000110, /* lots of values here */ , 12'b111111111001};   always @ (posedge clk or negedge rst)  begin  for (i = 0; i <= 2047; i = i + 1)  begin  assign RAM_2048_12BIT[11:0] = my_rom[11:0];  end  if (!rst)   data <= 12'b0;   else   if(clk)   begin   temp[10:0] = addr;   data = RAM_2048_12BIT[temp];   end   end   endmodule  And when I compiled it, I got an error: "Error (10053): Verilog HDL error at rom_sin.v(274): can't index object "MY_ROM" with zero packed or unpacked array dimensions" Please tell me why this error occurs and how to fix it. Thank you so much!

[Altera_Forum]

Where is the declaration for MY_ROM? 

 Also, you should not put a range in the select if you don't need it.   assign RAM_2048_12BIT[11:0] = my_rom[11:0];  When you put in a range, it makes me thing you are only selecting part of the memory  Without the range it says your intent is to pass the whole element.   assign RAM_2048_12BIT = my_rom;