Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

a problem with gate-level simulation of stratix3

Altera_Forum
Honored Contributor II
‎08-28-2009 08:32 AM
986 Views

when i implement a gate-level simulation of stratix3 device , 

with quartus 8.1 and modelsim 6.3g,  

i came across six document: 

 

pll_dco_3_1100mv_0c_slow.vo 

pll_dco_3_1100mv_85c_slow.vo 

pll_dco_min_1100mv_0c_fast.vo 

pll_dco_3_1100mv_0c_v_slow.sdo 

pll_dco_3_1100mv_85c_v_slow.sdo 

pll_dco_min_1100mv_0c_v_fast.sdo 

(pll_dco is the project name) 

 

i have not met these documents, 

(only kowns <project name>.vo 

and <project name>_v.sdo) 

 

Thanks! 

 

i want ask : 

what are their usage, 

and the method to use them.
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.