about clock gating

[Altera_Forum]

hi all: 

 I have a design on Cycloneiii. I am now trying to implement clock gating to reduce power.    design itself: There is a PLL lock the external clk through the pin, and generate a clk signal to all the ff in the design. The design has lots of entities (about 20) connecting each other. All the entities work in a serial way, which means, after one entity finish its job, it passes the result to another entity.    clock gating unit: 1, using VHDL to define an entity, which has one latch (or ff), an AND gat; two inputs (ena, clkin), one output (clkout). I think most of you are fammiliar with this structure~~~ 2, using the ALTCLKCTRL core of Cycloneiii, disabling the clock select function (clkselect), enable the buffer control (ena) to gate the input clock signal.    how to implement: After the clk out of PLL, before the clk goes into each entity, I plan to add a clock gating unit on the clk path. They are controlled by the some status signals of the entities dynamically.    question: I have some problems in the gate-level simulation. I don't think the compiler can handler the clock paths with AND gate in them well. How to solve it?? I am not it is the proper way of clock gating. If it is not, then what it should be??   looking forwards for responds~~~~

[Altera_Forum]

this solution has some good insight on CLKCTRL vs using the clock enable on the actual registers (which is preferred to gating the actual clock signal). 

 http://www.altera.com/support/kdb/solutions/rd09292006_400.html

[Altera_Forum]

--- Quote Start ---  this solution has some good insight on CLKCTRL vs using the clock enable on the actual registers (which is preferred to gating the actual clock signal).  http://www.altera.com/support/kdb/solutions/rd09292006_400.html  --- Quote End ---      thanks first. But I think clock enable is not as good as clock gating due to the reason described on that link. That is why I stick on clock gating.

[Altera_Forum]

--- Quote Start ---  thanks first. But I think clock enable is not as good as clock gating due to the reason described on that link. That is why I stick on clock gating.  --- Quote End ---    Hi,  what kind of problems do you have in your gatelevel simulation ? Any timing violations in your timing reports ? How many gated clocks do use ? How many registers are driven by the different gated clocks ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,   what kind of problems do you have in your gatelevel simulation ? Any timing violations in your timing reports ? How many gated clocks do use ? How many registers are driven by the different gated clocks ?   Kind regards   GPK  --- Quote End ---     The gate level simulation error is that I didnot receive the expected number of data. I think it is becasue the local clock signals are not synchronous. So when the two entities communicate, they may miss the message between them.  There are timing violations of holding time. I have used about 20 clock gating units, each of them drives all the registers of a certain entity (maybe 20~40 ff). And some of the entities are RAM and FIFO.    Best

[Altera_Forum]

--- Quote Start ---  The gate level simulation error is that I didnot receive the expected number of data. I think it is becasue the local clock signals are not synchronous. So when the two entities communicate, they may miss the message between them.  There are timing violations of holding time. I have used about 20 clock gating units, each of them drives all the registers of a certain entity (maybe 20~40 ff). And some of the entities are RAM and FIFO.    Best  --- Quote End ---    Hi,  what kind of FPGA are you using ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,   what kind of FPGA are you using ?   Kind regards   GPK  --- Quote End ---       Altera Cycloneiii

[Altera_Forum]

--- Quote Start ---  Altera Cycloneiii  --- Quote End ---     Hi,  how large are your holdtime violations ? Please check :  Assignments -> Settings -> Fitter Settings   that under "Optimize Hold time " "All paths" is selected. If not, change the setting and re-run Quartus.  Kind regards  GPK