altclkctr ip error when i supply two clocks (no PLL) that i'm trying to mux between

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Hi All, 

 really appreciate any kind of help regarding this issue,  the error i receive is:  Error (176375): Can't place Clock Control Block bc_gpiopld:karkom_bc_gpiopld|pch_bios_to_7seg_espi_lpc_if_unit:espi_lpc_unit|clkmux:clkmux_inst|clkmux_altclkctrl_7ji:clkmux_altclkctrl_7ji_component|clkctrl1 in location <nothing> -- location conflicts with source nodes of inclk ports  Info (176376): Placed node C_PCH_GPP_A_10_CLKOUT_LPC_1_RR~input in location PIN J28 (CLK5, DIFFCLK_2n)  Info (176377): Clock Control Block can be placed at location CLKCTRL_G7  Info (176377): Clock Control Block can be placed at location CLKCTRL_G6  Info (176376): Placed node C_CLK_HKSCLK_FPGA~input in location PIN J1 (CLK1, DIFFCLK_0n)  Info (176377): Clock Control Block can be placed at location CLKCTRL_G2  Info (176377): Clock Control Block can be placed at location CLKCTRL_G1  i don't understand the error message and the help by altera:    CAUSE: The Fitter cannot place the specified clock control block (http://quartushelp.altera.com/12.1/mergedprojects/reference/glossary/def_clk_ctrl_block.htm) due to conflicts with the locations of the nodes that feed the inclk ports of the Clock Control Block. This error can occur when the location of the inclk port source nodes prevent the nodes from being able to feed a Clock Control Block. Click the + icon to display details on the location of the source nodes for the inclk ports of the Clock Control Block.   ACTION: Assign the Clock Control Block or the source nodes of the inclk ports so that the source nodes can feed the inclk ports of the Clock Control Block.     i was under the impression that i supply two clocks and select net again both none PLL   the device i use is Cyclone IV E: EP4CE30F29C8 on quartus version 13.1  Thanks,  EA

[Altera_Forum]

How did you solve?  

 Thanks,  Joseph