altlvds_rx ModelSim simulation missing data

[Altera_Forum]

I have a simulation that consists of an altlvds_rx block with an external PLL. Every block in the system looks to be functioning correctly, except the altlvds_rx block which looks to have all the correct signals going in, but only zeroes going out. I was wondering if anyone knew what might be causing this when the testbench worked fine before Quartus 15.1? Having an external PLL, the block is supposed to be clocked by that, so I can see hard-coded timing as being an issue, but I'd definitely like to hear if anyone else has had issues simulating the block and might have some ideas. 

 On-chip the module works great.

[Altera_Forum]

I've had problems using the altlvds_rx with external PLL in simulation as well. There is an issue with the simulated PLL that causes one of the internal counters (I forget which one, maybe C) to be out by 1 count which means that the clocks are out of phase. It took me a long time to figure out that it was the simulation model causing the problems rather than the calculations in the ALTLVDS datasheet. 

 I never found a satisfactory work around. To get it to work I ended up having to adjust the phase of one of the clocks in the simulation. The trouble is it's been two years since I did the simulation, so can't remember how I made it work. I'll try to see if I have any old testbenches from a couple of years with the changes in.

[Altera_Forum]

I can definitely say that this is not what I would have expected! That's great to know, though, and explains quite a bit. Well, let me know if you find out the issue. 

 Have you put an SR in for this with support? Maybe we could get Altera to fix the simulation model.

[Altera_Forum]

In the end I gave up (this was 2 years ago), and just verified it was working using hardware and SignalTap.

[Altera_Forum]

--- Quote Start ---  In the end I gave up (this was 2 years ago), and just verified it was working using hardware and SignalTap.  --- Quote End ---    At least it works-- thanks for the information.

[Altera_Forum]

After considerable struggles with PLL simulations, I've decided to just write code in my test bench to generate the desired clock signals. It's much easier than working with problematic simulations.