Hi
I am facing problems when including altsyncram blocks with ENABLE_RUNTIME_MOD=YES parallel to the SFL. I'm not sure if this is Quartus version dependant, I only tried 9.1 so far.
If I enable the runtime modification (the only change) I first get to more warnings:
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Warning: Node: jtag.bp.tagInst_altsyncram_component_auto_generated_mgl_prim2_raw_tck was determined to be a clock but was found without an associated clock assignment.
Warning: Node: jtag.bp.flashLoaderInst__DEFAULT_PGM_sfl_inst_raw_tck was determined to be a clock but was found without an associated clock assignment.
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Then, the timing analyzer complains about latches that the synthesis didn't report with a funny name:
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Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "_no_real_name_" is a latch
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There are 21 of these latches for the timing analyzer. I couldn't find them in any netlist viewer.
Last but not least, the timing analyzer fails to recognize any sdc statements that work fine without the runtime modification.
Did anyone see similar problems? Is that a bug?
Thanks,
emanuel
