annoying warning during synthesis.

[Altera_Forum]

Hi 

During synthesis I get a lot of warning saying: "Warning: Using design file some_name.vhd, which is not specified as a design file for the current project, but contains definitions for X design units and Y entities in project"  My project files are stored in libraries, and in the project settings I add the path to these libraries. the Quartus manage to find the files using these paths, but still generates these annoying warnings that clatter my reports.  What is the best way to define the path to each path? I hope I don't have to do it manually because I have a lot of them..  thanks in advance

[Altera_Forum]

its picked up the file that you are using but have not specified as a project file. To get rid of this warning you will have to add all library files to the project file list.

[Altera_Forum]

I'm afraid you must keep on enduring those annoying warnings. 

This is a known issue. It has been discussed in another thread some time ago and someone advanced a solution to avoid the warnings. But, if I remember correctly, it was only a partial solution and it involved some extensive work to reorganize project file and paths, so I never tried myself. If you are interested, try search the forum.

[Altera_Forum]

--- Quote Start ---  Hi During synthesis I get a lot of warning saying: "Warning: Using design file some_name.vhd, which is not specified as a design file for the current project, but contains definitions for X design units and Y entities in project"  My project files are stored in libraries, and in the project settings I add the path to these libraries. the Quartus manage to find the files using these paths, but still generates these annoying warnings that clatter my reports.  What is the best way to define the path to each path? I hope I don't have to do it manually because I have a lot of them..  thanks in advance  --- Quote End ---    You have to add every 'user' .vhd (and .v, .tdf etc.) to the "Files" section under Settings. If you use .tdf files which include user .inc, then you must add the path of the .inc files to "Libraries" section.

[Altera_Forum]

You can suppress messages, including these warnings. It's a one time thing and then done. Right-click on them, I believe. 

The reason its a warning is that the files are picked up implicitly(from what I've seen, very few tools let you do this), and though allowed, not the best practice. For example, I've found very few people that use this know its rules for finding a file and adding it. As long as only one file exists with the proper entity/module, it's fine since the worst thing that could happen is that it doesn't find the correct file, but if there are multiple files with the same entity/module, it can get a little dangerous, although to be honest, I've seldom heard of problems.

[Altera_Forum]

Oh, and the reason it's a warning is for the user who wants to add everything explicitly, which is considered the safer practice. That way they don't see the warning at all, but when it does show up, they know to look at it. So it can be very helpful(i.e. I wouldn't want it to go away).

[Altera_Forum]

--- Quote Start ---  Oh, and the reason it's a warning is for the user who wants to add everything explicitly, which is considered the safer practice. That way they don't see the warning at all, but when it does show up, they know to look at it. So it can be very helpful(i.e. I wouldn't want it to go away).  --- Quote End ---   I got used and even learned to appreciate to have to specifically add all user files to get rid of these warnings. Do you have a similarly correct way of getting rid of all the warnings generated by Altera IP? E.g a typical Qsys system (NIOS II, DDR2 HPC , SGDMA , TSE) generates almost a thousand 'Verilog' warnings, so whining about these 'Using design file xxx ..' warnings is almost academic (with excuses to Dave).

[Altera_Forum]

Ugh. Sorry, but not an easy one. In justification: 

- It is difficult to write IP that has no warnings, but parameterized IP is significantly more difficult. (It's just too easy to let synthesis reduce a bus to the correct size of something like that). - It is difficult to say a warning is all right under all conditions. We don't want to do a blanket suppression, as there may be cases where the user has hooked something up incorrectly, and the warnings in the IP are what would identify that. Although with too many warnings, it's probably too difficult to know what's real and what's not. Anyway, it's difficult, but Altera should do a better job of it, no doubt about it. I know this is always on the radar, but not sure what/when will happen.

[Altera_Forum]

--- Quote Start ---  Ugh. Sorry, but not an easy one. In justification: - It is difficult to write IP that has no warnings, but parameterized IP is significantly more difficult. (It's just too easy to let synthesis reduce a bus to the correct size of something like that). - It is difficult to say a warning is all right under all conditions. We don't want to do a blanket suppression, as there may be cases where the user has hooked something up incorrectly, and the warnings in the IP are what would identify that. Although with too many warnings, it's probably too difficult to know what's real and what's not. Anyway, it's difficult, but Altera should do a better job of it, no doubt about it. I know this is always on the radar, but not sure what/when will happen.  --- Quote End ---    I'd say as an apology, rather? Relying on the synthesizer to reduce a bus to the correct size and not bother about the warning is pure laziness. Do not forget that the poor user has to search the messages for those warnings he's responsible for. And I always ponder whether those Altera warnings are benign or not, and whether it is me triggering them. Remember the old C-adagio: a warning is an error waiting to happen. And personally I don't think it is difficult to write warning free code (even parametrized) , it may be a bit more work though. Blanket suppression of Altera (and others!) IP generated warnings may be not that good idea, but you don't expect me to wade through all 1000 warnings on every compile? An idea: maybe Altera can create a 'user warning' class with associated colour for warnings triggered by 'user' code?

[Altera_Forum]

--- Quote Start ---   An idea: maybe Altera can create a 'user warning' class with associated colour for warnings triggered by 'user' code?  --- Quote End ---    You mean something like "suppress by entity"?  can I add a file to the libraries so when I add the library to the project it will automatically add all the files? I believe .qip files do something similar for components generated by automatic tools.  as you mentioned I don't want to do a blanket suppression, but I'm not thrilled about including every single file either...

[Altera_Forum]

No, a separate warning class so we can recognize the warnings generated in our 'user' code from the ones generated by Altera and Third-Party IP. 

 .qip files are good idea, especially if you want to include a subtree of code. and .qip files can reference other .qip files.  They are text files so you can make your own quite easily. Again you add the .qip file to the "Files" section.

[Altera_Forum]

Bus width reduction is easy to avoid, I was just using it as an example, when blocks have many, many parameters, all adding/removing logic and changing port lists, it can be quite complicated. Again, it should be better. As for identifying "user generated" warnings, that's the problem, in that there is no way to tell what is user generated.  

 For "the brick", the library term is a little misleading. In Quartus II, User Libraries is nothing more than a search path. So if an entity instantiates something called "ingress" for example, then Quartus II will first search all files manually added to see if they have a module/entity. Then it searches the project directory and all search path directories to see if they have a source file with that name, such as ingress.v, ingress.vhd, ingress.bdf, etc. (Note that if the file name doesn't match, such as a file called ingress_revB.v, it won't be looked at). VHDL has a whole different set of libraries with a different meaning. A .qip is just a Tcl-like file that is generally used to add files, but since they're in a file, they're held together, i.e. all the files are either added or not. The other benefit of a .qip is that it can reference where it's at, and add the files relative to it. That allows the user to move the .qip and the source files around, and as long as they keep their relative locations, it works.  My feeling is to go to Project -> Add Files and just start adding files you know you use. If you spend 15 minutes, I imagine you'll get a significant chunk. Then start looking at the warnings, and add what keeps coming up over time. They'll all be in the .qsf, and if you want, you can cut and paste them into a .qip, and do a search and replace to make them relative paths. Unless you have thousands of files in different hierarchies(which is possible), it's usually not too much trouble.

[Altera_Forum]

--- Quote Start ---  Bus width reduction is easy to avoid, I was just using it as an example, when blocks have many, many parameters, all adding/removing logic and changing port lists, it can be quite complicated. Again, it should be better. As for identifying "user generated" warnings, that's the problem, in that there is no way to tell what is user generated.  --- Quote End ---   I knew the bus reduction was just an example ... but I still don't see why any of the other 'complexities' warrant the uncontrolled proliferation of so many warnings. Like I said it is not just Altera, I have used IP of other parties as well and that produced a equally insane amount of warnings. So you ignore them and just hope your HW test or simulation (for the brave ones who simulate their top-level design) works.  If we can not better identify the 'user generated' warnings we have a strong case for the abolishment of those IP-generated warnings!  -- added -- It just came to mind that it is the 'encrypted IP' that generates most of the warning mess. Here I can understand that it is difficult to avoid warnings as you can not easily re-generate encrypted code if the user can choose between e.g. GMII, RGMII, of SGMII connections. Then again with a bit of effort this should be possible too.

[Altera_Forum]

Rysc I believe I have a few hundreds of files, so it is quite a tedious job, even worse, if I use the same libraries in several projects, I'll have to do it all over again. the .qip will solve that problem, just add one file (instead of adding the library. 

 you are correct that I use the term library in the "search path" sense, not VHDL sense.

[Altera_Forum]

Yes, that's definitely a pain. Good luck. Be sure to look at the .qip syntax from a piece of IP to see how they join the path to the .qip with the underlying HDL.

[Altera_Forum]

i have a bash script that creates .qip files by parsing the directory for files with a certain extension that i could share

[Altera_Forum]

--- Quote Start ---  i have a bash script that creates .qip files by parsing the directory for files with a certain extension that i could share  --- Quote End ---    I for one would appreciate it.

[Altera_Forum]

Hi 

 I have just encountered another related issue. in my .qsf file some of my asignments looks like:   --- Quote Start ---   set_global_assignment -name SEARCH_PATH sub_dir/sub_sub_dir   --- Quote End ---  But some looks like:   --- Quote Start ---   set_global_assignment -name SEARCH_PATH "sub_dir/sub_sub_dir"   --- Quote End ---  When I try to remove the quotation marks, as soon as I switch back (I perform the change in a text editor) to the Quartus window I get a pop up error message saying something like: "The qsf file was changed and contains errors, reverting to saved version"  Can anyone please explain to me what I'm missing here?   Found it - there was a space in the library name  This is a problem because I want to copy and paste from a project to a higher level project (after adding the first project path of course)  Thanks

[Altera_Forum]

I had some trouble with running bash file so I ended up using a tcl script to list all of the source files that are in project folder (and sub folder) 

 I copied the script from this book (http://www.beedub.com/book/tkbook.pdf): Example 7–12 Finding a file by name