arithmetic mode for LE from vhdl

Altera_Forum · ‎11-01-2015

I have searched many threads for the solution and the answers were incomplete. So i try to do some investigation.

this code in vhdl definitely put your counter in arithmetic mode for LE. if you have any suggestion please share it with me.

process(reset, clk, count_en)
        variable v : unsigned(cnt_reg'length downto 0);
    begin
        if reset = '1' then
            cnt_reg <= (others => '0');
            cnt_full <= '0'; -- it means counter foolish your 
        elsif rising_edge(clk) then
            if count_en = '1' then
                v := ('0' & cnt_reg) + (to_unsigned(0,v'length-1) & count_en); -- if you add with constant you cannot get arithmetic mode for LE
                cnt_reg <= v(v'high-1 downto 0);
                cnt_full <= v(v'high);
            end if;
        end if;
    end process;

Altera_Forum · ‎11-01-2015

it seems that the very first LE do not use carry-in but it may . So the quetion is how to put a 'one' on the very first LE to cin input.

ps : the last element in counter (at msb) could run in arithmetic mode, but you should read the overflow counter value otherwise it run in normal mode.

Altera_Forum · ‎11-01-2015

It can only use the cin if count-en is generated on a LE in the same LE column so that it can put the signal on the carry chain, which I assume it isn't.

Why do you use count en as the add word? This will just get converted to logic 1 because the register only enables the the input when enable is 1, hence you always add 1.

Altera_Forum · ‎11-01-2015

Tricky, you are right. But I was gleeful about the code above. Even if it is ugly and count only by one. I'l try my best )

Altera_Forum · ‎11-01-2015

--- Quote Start ---

It can only use the cin if count-en is generated on a LE in the same LE column so that it can put the signal on the carry chain, which I assume it isn't.

Why do you use count en as the add word? This will just get converted to logic 1 because the register only enables the the input when enable is 1, hence you always add 1.

--- Quote End ---

okay. LE cin input accessable only by another LE. if i am wrong correct me.

I don't know why quartus doesn't aware construction like cnt <= cnt +1 as signal to itself for turning on arithmetic mode at synthesis. So it was a tricky with code so quartus able to turn on arithmetic mode automatically. btw, any arithmetic operations with constant don't turn on arithmetic mode.

process(reset, clk, count_en)
        variable v : unsigned(cnt_reg'length downto 0);
    begin
        if reset = '1' then
            cnt_reg <= (others => '0');
            cnt_full <= '0';
        elsif rising_edge(clk) then
            if count_en = '1' then
                v := resize(cnt_reg, v'length) + (to_unsigned(0, cnt_reg'length) & count_en);
                cnt_reg <= resize(v, cnt_reg'length);
                cnt_full <= v(v'high);
            end if;
        end if;
end process;

Altera_Forum · ‎11-01-2015

Can I try and understand why you are doing this?

A constant is "free" when it comes to timing. Using an input like about would just increase the amount of routing required, so technically slower and use more resources.

Altera_Forum · ‎11-02-2015

Why? Cause I want so and i have no table with results to compare.

I know about adding a constant to register. will it better to change to 4 input LUT-function only without Carry-propagate function and use register feedback? are there any benifits from normal mode when doing arithmetic operation with constant? What about "use more resources" -> quantity of LE remains for normal or for arithmetic mode, does'nt matter. LE becomes 2 separate 3inputLUT for sum and for carry but is still in one LE.

but my main idea was "quartus able to turn on arithmetic mode for LE from processing vhdl code". It definitly turns on arithmetic mode with non-constant drivers when using arithmetic operaions <- counter outputs is good candidates to unstabe category.

Altera_Forum · ‎11-03-2015

it is said about device arhitecture "LE carry chains—carry chains propagated serially through each LE within a LAB".

and Tricky said "it will be slower".

will it be ripple? if yes, what will be the reasonable width for such counter so we won't degradade in perfomance.

how to measure ratio for frequencies Fripple/Fclk. and we can divide long counter to some smaller ones.

Altera_Forum · ‎11-03-2015

I was refering to using a constant rather than using the enable signal into the carry chain.

The constant requires 0 routing, hence zero timing impact.

The enable signal needs to be routed in somehow, and will add some routing delay.