- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I know the following line is possible in SystemVerilog and Verilog: `define SQRT_2 $sqrt(2) But, I want to do the following: `define MY_CONSTANT $my_defined_function(5) Does anyone know if is it possible? Thanks.Link Copied
0 Replies

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page