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assign `define macro with user function

Altera_Forum
Honored Contributor II
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Hello, 

 

I know the following line is possible in SystemVerilog and Verilog: 

`define SQRT_2 $sqrt(2) 

 

But, I want to do the following: 

 

`define MY_CONSTANT $my_defined_function(5) 

 

Does anyone know if is it possible? 

 

Thanks.
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