I was dealing with an issue for a while, and it turns out that a part of it was that some of the bit mappings were changed while switching from quartus version 16.1 to 20.1 pro. (in this case, lanes were mapped diffrenetly while in the jesd204b ip)
now I seem to have a similar issue with the ip "Triple-speed ethernet intelfpga ip"
I couldn't find anything about it in the release notes,
is there a place where I can see this change, both to confirm this, but also to able to reduce debug time?
Hi, Thanks for your update. I understand that you have mentioned two IPs in the description. To ensure we are on the same page, just would like to check with you if you are currently trying to debug into the TSE IP or JESD IP? This is so that we could engage the right team to provide better assistance. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.