can't find 'clk' pin using get_pins in timequest timing analyzer

[Altera_Forum]

using quartus 11.1 build 216 w/service pack 1. My design uses LPM_ADD_SUB components, with the results output registered (not the pipeline registers in the component). I am trying to do report_path in timequest timing analyzer, to see the delay from my clock pin to one of the registers that is at the output of the LPM_ADD_SUB's 'result' output pin. However, when I try to find the 'clk' pin using the name finder, I can't see the 'clk' pins - only the datapath pins to the LE associated with the register. In chip planner, I can clearly see the registers, so I know they are there and not optimized away. 

 has anyone else had this problem? any solutions?

[Altera_Forum]

Something llike get_pins *|clk works for me..

[Altera_Forum]

yes, I tried that - doesn't find the pins I'm looking for. it's a tool problem or an optimization problem. I was hoping that someone else had a similar problem and found a workaround.

[Altera_Forum]

I have the same problem but with Version 9.1SP2. (I have to use this rather old version, since recent versions don't accept my pci licenze file). 

 I want to specify a generated_clock timing constraint.  With:  get_registers {*|registername} I get the register i want.  But if I use get_pins {*|registername|clk} I get the warning that the filter coudn't be matched.  Any ideas?

[Altera_Forum]

Well, my situation turned out to be a register that wasn't driving anything. In the process of creating my design, I had registers that were not driving any logic or outputs. I think this is a bug in the timing analyzer. 

 If this is your situation, either send the output of the register to a pin on your device, or create a virtual output and drive that.

[Altera_Forum]

Thanks for your reply. 

I once had the same problem as you. (registers driving no logic) I solved this by using the synthessis attribute noprune.  signal registerIwantToKeep : std_logic; attribute keep : boolean; attribute keep registerIwantToKeep : signal is true;

[Altera_Forum]

The experience I had was that, even if I put attributes like 'preserve' or 'noprune' on the register, sure the register would not get optimized away. however, you could still not find the 'clk' pin in the timing analyzer. I think this is a bug in the tools. 

 Response from Altera to one of my service requests:  'Thank you for letting me know. The software engineer has confirmed that the register with no fan-out is eliminated from the timing netlist. This is why you aren't able to locate the register and the input/output pins of the reigsters. He said this is by design, so in order to work around this, you would need to have the register's output driving something (as you are doing now).'