cascade of 2 counters

[Altera_Forum]

Hi all, 

sorry to post a so simple question but I'm blocked on this and I don't know how to solve it: I have a custom board with a Stratix II GX on it (S2GX), a 40 Mhz clock provided to it and 12 leds. The arriving clock is fed to a PLL which outputs a "clear" 40 Mhz freq. (this I have to do for another reason, but I have to) My aim is to light up 1 led / second, after 12 sec have all the leds turned on. I thought to do it with 2 cascaded counters: the first counts up to 40.000.000 (clk freq), its carry_out signal is the clock for the second counter, which counts up to 12. The value of this second counter is the control signal for my leds. For both the counters I used the LPM_Counter megafunction. When I run analysis and synth everything is ok, but with full compilation I get a critical warning:  Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.  and I can see a negative slack time on the summary of the timing analyzer for PLL's Clock hold.   I don't know if it's a good idea to post code, owing to my use of the megafunctions, in case I can do it. Anyway, any idea / suggestion / help would be REALLY appreciated, thanks since now,  C.

[Altera_Forum]

I see that you've already looked at http://www.alteraforum.com/forum/showthread.php?p=8500. If your clock hold violations are for synchronous cross-domain paths between the cascaded counters, then try using the output of the first counter as a clock enable (not a clock) for the second counter. 

 If you are using the Classic Timing Analyzer, look at the compilation messages giving the results of the path with the worst hold violation, or right click the worst path in the Clock Hold report table and select "List Paths" to get these messages. Expand all the messages until you see the details of clock skew. This will show you what is causing the hold violation. If the violation is because of your ripple clock, you will see the ripple clock in the clock path for only one of the data registers.  You can see similar information in TimeQuest. Use Report Timing on a hold violation using the "-detail full_path" option so that you can compare the clock paths for the source register in the data arrival path and destination register in the data required path. In the GUI, the Report Timing "Statistics" tab will show a summary of the clock skew, which is probably large for your hold violations.

[Altera_Forum]

Hi Brad, 

and thanks for the answer: in fact I read your post, it was really useful! I got rid of those error messages, and also learned some interesting stuff. Really a good post!  Also this post from you is useful to me, now I have my (simple) project compiled at 100%, I'm getting more support from this forum than from altera directly! Thanks again. C