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Altera_Forum
Honored Contributor I
799 Views

compiler can't fit design despite 1st stage compile reporting low utilization

I'm attempting to compile a kernel for an Arria 10 device. The 1st stage compile completes and reports the following utilization: 

 

ALUTS: 31% 

FFs: 33% 

RAM: 44% 

DSP: 10% 

 

Despite the design easily fitting into the part, the fitter fails with an errors message saying " Error <170048>: Selected device has 2713 RAM locations of type M20K block. However, the current design needs more than 2713 to successfully fit". 

 

Why such a large discrepancy between the resource utilization reported during the 1st stage compile and fitting?
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2 Replies
Altera_Forum
Honored Contributor I
19 Views

The estimated resource utilization reported after the first stage of compilation is based on Altera's OpenCL model (and not even post-synthesis area utilization) and on Arria 10 I have encountered cases where logic and memory utilization were even 50% off. Modelling area utilization is not easy when the design has not been synthesized, even for Altera, so such discrepancies are expected. Unfortunately there is no way other than full placement and routing to get accurate resource utilization.

Altera_Forum
Honored Contributor I
19 Views

You can try to use the latest 17.0 SDK, as there are some resources management improvement made. 

 

Regards, 

CloseCL 

(This message was posted on behalf of Intel Corporation)
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