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Altera_Forum
Honored Contributor I
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concurrent host and device memory accesses

I'm attempting to implement a design where I'd like the host to be able to perform memory reads while the kernel is running. Essentially I have a continuous data stream coming from a channel sourced by my boards 10GBE interface. The data is processed via a number of computational kernels before being written to global memory. The post processed data needs to made available to the host without ever stopping the active kernels. Does Altera's OpenCL framework support this type of operation?

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Altera_Forum
Honored Contributor I
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If your board supports host channels (which have been supported in Altera's reference board since v17.1), you can use that. If not, considering the fact that OpenCL only guarantees global memory consistency after full kernel execution, there is no way to know when the data in the FPGA external memory is valid during kernel execution to read it on the host. However, you might be able to get it to work by having two buffers on the FPGA external memory, and a separate kernel writing to each. In this case, you will first write the processed data to buffer A, switch to buffer B while the host is reading from buffer A, then switch back to buffer A when the host is reading from buffer B, and so on. Essentially, double-buffering. Though this will not guarantee uninterrupted processing and hence, you will need a back pressure mechanism for the network connection (there will never be any guarantee for uninterrupted processing, even with host channels; hence, you will need back pressure anyway).

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