continuous averaging using VHDL

[Altera_Forum]

I have a question related to VHDL programming. I want to calculate the continuous average. My example code is: 

  process (clk, reset) begin if (reset = '1') then state<=idle; out-val=0; elsif(rising_edge(clk)) then case state is when idle => if req='1' then state= out-1; end if; when out-1 => if done='1' then out-val<=data-in (11 downto 0) state <= done-st; endif; when done-st => ack <='1'; state <= idle; when others => state <= idle; end case; end if; end process;   On every positive edge of clock, the value of "out-val" changes. I want to continuously take the average of "out-val". I want to take average of 32 values continuously. Is there a way where I can take average of 32 values continuously till the clock is running. Kindly let me know how can I do that. You can modify the above code as well. Many Thanks,

[Altera_Forum]

--- Quote Start ---  @kaz,  I have figured it out that my average block was not running at all because I was running it at 20MHz and the done signal coming from SPI block is running on 78KHz which means I get the next data_in after every 78KHz. I am now running my average block on CS (78kHz) coming from spi master instead of normal clock of 20MHz. Now I am getting the result like before i-e 10mA, 20mA, 40mA,......100mA and the value gets stable after that. I am not sure but I think I need to further divide down the CS to 39KHz to get the 100mA directly. Am I right?  --- Quote End ---    The filter sampling rate must be exactly that of adc 12 bits data rate i.e. 19.5 KHz (if I am remember it correctly).  The sampling rate of a module is the clock rate as modified by any applied clock enable. The best action is to simulate the filter on its own using the matlab model I posted and to simplify it you may inject a constant or any simple stream into both your design and matlab model and compare. They must match bitwise.

[Altera_Forum]

--- Quote Start ---  The filter sampling rate must be exactly that of adc 12 bits data rate i.e. 19.5 KHz (if I am remember it correctly).  The sampling rate of a module is the clock rate as modified by any applied clock enable. The best action is to simulate the filter on its own using the matlab model I posted and to simplify it you may inject a constant or any simple stream into both your design and matlab model and compare. They must match bitwise.  --- Quote End ---    @kaz Ok I will check in MATLAB as well on monday. The data sheet link for the ADC that I am using is:  http://www.ti.com/lit/ds/symlink/adc122s021.pdf  If you see the data sheet for ADC, I previously thought that SCLK is 312KHz and if you see the timing diagram for ADC in the data sheet, it has a burst of 16 SCLK cycles so I came up with sampling rate of 312.5KHz/16=19.5KHz. But actually i was wrong. I checked it and the SCLK is 1.25MHz which means that the data rate should be 1.25MHz/16=78.125KHz or may be I think if you see the timing diagram in the ADC data sheet, there is an extra 4 SCLK cycles before the next burst comes out which means that filter sampling rate should be 1.25MHz/20= 62.5KHz. It means my average filter block should run on clock=62.5KHz according to timing diagram in data sheet(page 6 in the data sheet). Am I right? May be then I will get the 100mA directly instead of slow increment.

[Altera_Forum]

--- Quote Start ---  @kaz Ok I will check in MATLAB as well on monday. The data sheet link for the ADC that I am using is:  http://www.ti.com/lit/ds/symlink/adc122s021.pdf  If you see the data sheet for ADC, I previously thought that SCLK is 312KHz and if you see the timing diagram for ADC in the data sheet, it has a burst of 16 SCLK cycles so I came up with sampling rate of 312.5KHz/16=19.5KHz. But actually i was wrong. I checked it and the SCLK is 1.25MHz which means that the data rate should be 1.25MHz/16=78.125KHz or may be I think if you see the timing diagram in the ADC data sheet, there is an extra 4 SCLK cycles before the next burst comes out which means that filter sampling rate should be 1.25MHz/20= 62.5KHz. It means my average filter block should run on clock=62.5KHz according to timing diagram in data sheet(page 6 in the data sheet). Am I right? May be then I will get the 100mA directly instead of slow increment.  --- Quote End ---    you don't need to compute the adc sampling rate. That is job of your design. Your logic that captures the 12 bits from adc must automatically get the adc rate and you apply that rate(in logic, not by your figures) on the filter. It should then be whatever it is, possibly 1.25MHz/16 and I don't see how you got the figure 20. Anyway it is up to your logic to work out the sampling rate and you don't need to even know the rate.

[Altera_Forum]

let me give my opinion so you can sort things out after all. 

use sclk through design. apply sclk to filter but clock-enabled on a pulse that indicates one adc 12 bit word is ready. take the 12 bit average and read it. that's all. Don't use two adc for now and don't use any state machine.

[Altera_Forum]

--- Quote Start ---  you don't need to compute the adc sampling rate. That is job of your design. Your logic that captures the 12 bits from adc must automatically get the adc rate and you apply that rate(in logic, not by your figures) on the filter. It should then be whatever it is, possibly 1.25MHz/16 and I don't see how you got the figure 20. Anyway it is up to your logic to work out the sampling rate and you don't need to even know the rate.  --- Quote End ---    Well I don't have the design with me now. I can check it on Monday. But what I tried today is that I was running my continuous average block on CS signal in the data sheet and the frequency for CS is 78.125KHz instead of normal clock of 20MHz and the result I get out of it was like before i-e 10mA, 20mA, 40mA,......100mA and the value gets stable after that. Is the for loop in the code increments on the rising edge of the clock?

[Altera_Forum]

--- Quote Start ---  Well I don't have the design with me now. I can check it on Monday. But what I tried today is that I was running my continuous average block on CS signal in the data sheet and the frequency for CS is 78.125KHz instead of normal clock of 20MHz and the result I get out of it was like before i-e 10mA, 20mA, 40mA,......100mA and the value gets stable after that. Is the for loop in the code increments on the rising edge of the clock?  --- Quote End ---    cs signal is only for activating adc and has nothing to do with data rate. You should use one clk(sclk) in your design. You should convert the 12 bits serial adc data to 12 bits word(parallel) and produce one pulse (for one sclk period) when word is ready then use this pulse to clock-enable the design.

[Altera_Forum]

I am puzzled now. What is then your data(11 downto 0)? isn't it adc data being converted as parallel word from the 12 bits serial stream? 

 sclk needs clock enable, where is your pulse that indicates data(11 downto 0) is ready? you need to put that pulse as if condition after sclk.  you really need to revise your thoughts carefully and write code yourself as otherwise we will stay going in circles. Good luck.