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Altera_Forum
Honored Contributor I
798 Views

cyclone V E dev kit programming failed in EPCQ mode

Hi: 

i an trying to use the cyclone v e dev kit to practice, < board update portal based on nios ii processor with epcq > example but it always failed at 95% when i programming the .jic in to the epcq. 

i have already changed configuration resistor r17 and r19. dose anyone know why ?  

thanks&#65281; 

 

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Altera_Forum
Honored Contributor I
46 Views

Hi, 

 

Did you test .sof file programming via JTAG configuration?  

1. If JTAG configuration with the .sof file is successful than it is the bitstream corruption issue. 

To check the bitstream try with some other .jic file of the simple project. 

 

2. If JTAG configuration with the .sof file is failed then it is the power issue. 

To check the Power issues you need to check the hardware side with respect to the cyclone v handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf) for POR session "Page 319". 

The goal is to achieve the POR requirements. 

 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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