daft question about Verilog parameter

[Altera_Forum]

Hi All, 

 Is it legal to define a new parameter based on a previously declared one ?  Thanks,  Mark  parameter HS64x8_XINC = 86; parameter HS64x8_X0POSN = 70; parameter HS64x8_X1POSN = (HS64x8_X0POSN+(HS64x8_XINC*1)); parameter HS64x8_X2POSN = (HS64x8_X0POSN+(HS64x8_XINC*2)); parameter HS64x8_X3POSN = (HS64x8_X0POSN+(HS64x8_XINC*3)); parameter HS64x8_X4POSN = (HS64x8_X0POSN+(HS64x8_XINC*4));

[Altera_Forum]

Yes you can do that. 

 I often do stuff like: module module_name# ( parameter BUS_WIDTH = 32, parameter BUS_WIDTH_DEC = clogb2(BUS_WIDTH) )( ports....   where clogb2 is a function so I can overload the parameter at the instantiation and have it propogate to the other parameter

[Altera_Forum]

Thank you very much

[Altera_Forum]

Oh boy... 

 I now have the problem where I change the parameter assignment within the Verilog source file, re-compile the entire project and discover that resulting module has the old parameter assignment. I can see this by looking at hierarchy, then mousing over the module name - a parameter list pops up for that module...  Almost sounds like a caching problem.  Any thoughts welcome.  -Mark

[Altera_Forum]

just found that if I rename all of the parameters (add an 'A' in the name etc.) this forces the correct values to be taken --- once

[Altera_Forum]

Just found the parameter within a BSF file, so the .V may need to have a new (updated) symbol file created every time you change a parameter...