Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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delay time of 50 - 200 ns from I to O without external clock

Altera_Forum
榮譽貢獻者 II
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Hey! 

 

I´m using Quartus II 13.1 Web Edition for a MAX V.  

I want to create a delay from 50 -200 ns from the input to output pin. I don´t want to use an external oscillator. The internal oscillator has a frequency of 15.6 to 21.2 MHz.  

Is it possible at all?  

 

I started trying it with a Block Diagram/Schematic File but had no success in this mentioned range. 

 

Regards! 

 

Johnsen
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Altera_Forum
榮譽貢獻者 II
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If you are satisfied with a rough and indeterminate delay in that range, you can simply add 2 or 3 cascaded registers clocked by the internal oscillator. 

On the other hand if you want an exact delay value in that range, and possibly adjusting it, you'll need an external (fast) clock. 

For example, if you want an adjustable delay in 20ns steps, you'll need a 50MHz clock. 

The delay is still achieved by passing the signal into a chain of N registers, but you must provide some logic to select N.
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