Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

differential signals on pins - schematic assignment

Altera_Forum
Honored Contributor II
‎08-15-2012 02:57 PM
1,191 Views

On the schematic I have an input named clock. In reality this should be a differential signal. Meaning, I should assign two pins instead of one. 

Likewise, I have LVDS outputs coming from an LVDS Megafunction. These are also single signals on the schematic. And they should have differential pins assigned. 

The Pin Planner somehow is not supporting this...
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎08-16-2012 05:32 AM
493 Views

As in HDL design descriptions, you'll connect the positive pin only in the schematic. The negative pin is assigned automatically by selecting a differential IO standard.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎08-16-2012 06:57 AM
493 Views

Thanks, that is somewhat counter intuitive and should be mentioned on a prominent place.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.