divide the internal clock

[Altera_Forum]

Hello 

 I'm trying to divide the intern oscillator to obtain a frequency around 1Khz.   LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; LIBRARY work; entity ClockGene is port ( osc : in std_logic; clk : out std_logic ); end entity; architecture arc of ClockGene is signal count : unsigned (12 downto 0); begin --count <= (others => '0'); impossible to synthetize --count <= "0000000000000"; process (osc) begin if rising_edge (osc) then count <= count + 1; clk <= count(11); end if; end process; end arc; But I can't simulate. error deleting "msim_transcript": permission denied

[Altera_Forum]

I know modelsim does not like free running binary counters. so just put a constraint at last count. 

 if count = 2**12-1 then  count <= (others => '0'); else...

[Altera_Forum]

you will also need to inialise count at declaration := (others => '0')

[Altera_Forum]

Ok thx it works. 

 I think there is a pb with count.  On modelsim I put a clock on osc and nothing happen for the 2 others.  Maybe I had to initialise count but I don't know how to do that.  I tried  count <= "0000000000000"but it didn't work.  edit: I'm too slow :) thanks

[Altera_Forum]

see my second post

[Altera_Forum]

--- Quote Start ---  I know modelsim does not like free running binary counters. so just put a constraint at last count.  if count = 2**12-1 then  count <= (others => '0'); else...  --- Quote End ---    There is nothing wrong with the origional code. Because the type is unsigned it will wrap around to 0 when it reaches 2**12-1. You only need to check for max if you are using an integer type.  The error is something to do with modelsim not having permission to delete some file. Not with the VHDL.  As an asside, the counter wont work unless it is reset or given some initial value.

[Altera_Forum]

My modelsim versions always issues error on binary counters without end constraint. 

 I know there is nothing wrong with that but we are talking about tools conduct rather than solid facts.

[Altera_Forum]

--- Quote Start ---  My modelsim versions always issues error on binary counters without end constraint.  I know there is nothing wrong with that but we are talking about tools conduct rather than solid facts.  --- Quote End ---    Ive never had a problem doing this, and Ive been using modelsim for 6 years. Its quite an important concept I use in a lot of places (especially memory addressing).

[Altera_Forum]

It depends on how many versions or setup issue we are talking about. 

 I am not making it up....it is too trivial to be an issue, isn't it?

[Altera_Forum]

--- Quote Start ---  It depends on how many versions or setup issue we are talking about.  I am not making it up....it is too trivial to be an issue, isn't it?  --- Quote End ---    Im talking about RTL simulation, unsigned + integer function. There is no way for this to cause any problems. The "+" function has no checking whatsoever for overflow. This function converts the integer to an unsigned, and then does the addition using xors and ands:   function ADD_UNSIGNED (L, R: UNSIGNED; C: STD_LOGIC) return UNSIGNED is constant L_LEFT: INTEGER := L'LENGTH-1; alias XL: UNSIGNED(L_LEFT downto 0) is L; alias XR: UNSIGNED(L_LEFT downto 0) is R; variable RESULT: UNSIGNED(L_LEFT downto 0); variable CBIT: STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end ADD_UNSIGNED;   So, there is NEVER a need to check for overflow on an unsigned type.

[Altera_Forum]

I know why I've had my first problem (modelsim and delete file). 

 It is very simple: modelsim must be closed when you want to export for simulation in quartus (if you have modified the same file).  I think we can just save the changement and reload in modelsim.  Now in my code I think I will use the library unsigned (I think) in order to let count in std_logic_vector.  But it works like that so...