Hi,
I am generating an Agilex7 example design with gen3 1x4 for AXI Streaming Intel FPGA IP for PCI Express. But every time in quartus prime pro 24.2, there is an error when compiling to analysis & synthesis:
Error(21978): The INCLK port on clock divide dut|dut|EP_PFTILE_WRAPPER.gen_pciess_p2_p3.u_pciess_p3|u_pciess|gen_sub.u_hipif|u_pciess_clock_divider|clkdiv_inst is connected to a constant. It must be driven by a real signal.
But this module is encrypted, so I can't know which clock is not connected.
Can someone tell me where I have set up the problem or if there are any other reasons?
Here is my setting parameter:
Link Copied
Hi ,
I try to run the example design in Gen 3 1x4, I am getting similar error as you.
BUT, this issue is not observed in Gen3 1x16.
There should be an error when generating/compile if it is not a supported ED.
If referring to AXI Streaming Intel® FPGA IP for PCI Express* User Guide under 3.4. About the AXI Streaming Intel® FPGA IP for PCI Express Design Examples
Obviously, Gen 3 1x4 is not in the option, hence the compilation fail is expected.
If your project requirement is not strict to gen3 1x4, I suggest you to consider other available option.
Hope that answered your question, let me know if there is any further clarification is needed.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
Hi Geats,
I am able to compile 100 % on Gen3 1x16 in Agilex F-series device.
For your device, You may need to do the pin placement accordingly based on your device OPN.
Because our design's example pin placement is only targeted F-series devkit
Detail about the pin placement you may refer to
- https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html
- https://cdrdv2-public.intel.com/666677/pcg-01023-683112-666677.pdf
Or you may refer to the design .qar in the attachment (for F-series) under .qsf file
You may re-use more then 60-80 % of the pin information.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
Hi Geats,
I also want to ask if I can use PCIe IP alone to generate Gen3x1 mode and only connect to refclk0 in this situation?
>> I never try this implementation before, perhaps you can give a try and see either the compilation is pass or not.
>> based on my understanding in most of cases, especially for simpler configurations like Gen3x1, connecting the reference clock to refclk0 alone is sufficient. This is because the PCIe IP core can operate with a single reference clock input for such configurations. I am not sure if this theory applicable the same to F-tile AXI Streaming or not.
Does this buffer require a specific IP core? Or simply generate it by user logic？
>> For buffer implementation, you may check
>> https://www.intel.com/content/www/us/en/docs/programmable/683780/22-3/i-o-buffers-and-registers.html
Hope that answered your question.
Regards,
Wincent
