Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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finding process operating on falling edge

Altera_Forum
名誉分销商 II
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Hi, 

 

in one design I am working on Quartus assumes transitions between rising and falling edges of one PLL clock, making life harder timing-wise. 

 

To my understanding, the reason why he would assume and find such transitions is the fact that somewhere in the design some process uses the falling edge of that clock (am I right?).  

 

Is there a way to find out - in TimeQuest - where the data is launched on the falling edge? 

The design is large, coding conventions (clock names, etc) are a disaster and "grep"-ing the design didn't bring me the process... 

 

Thanks!
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Altera_Forum
名誉分销商 II
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Run "Report Clock Transfers" to see numbers on all types of transfers(rr is rising edge to rising edge, rf is rising to falling, etc.). For specific paths, you can do: 

report_timing -setup -npaths 200 -detail full_path -rise_from * -fall_to * -panel_name "200 rise to fall transfers" 

This just shows rise to fall, regardless of clock. You coul also do: 

report_timing -setup -npaths 200 -detail full_path -rise_from_clock SRC_CLK -fall_to_clock DST_CLK -panel_name "rise of SRC_CLK to fall of DST_CLK" 

This will do it for specific clocks. You can combine these, do different rise/fall variations,etc.
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Altera_Forum
名誉分销商 II
422 次查看

Thanks Rysc! Another great answer :)

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