gate level simulations , wrong fmax

[Altera_Forum]

when i make gate level by linking modelsim simulator to quartus.  

the classic time simulator report that fmax = 170 MHz.  but on gate level the output would be true only at f = 100 MHz.  that is wrong?? i made full compilation and identify the clock bin as a clock ..

[Altera_Forum]

Is your testbench generating a 170 MHz clock?

[Altera_Forum]

i entered it form the wave form ..  

I tried f = 110 MHz  force -freeze sim:/testbench/clk 1 0, 0 {4500 ps} -r 9000

[Altera_Forum]

The Classical Timming Simulator only tells you that the desing Quartus produced will work at 170 MHz. 

 The frequency at which you are actually simulating the design is whatever you set in ModelSim: 110 MHz.

[Altera_Forum]

i know but if i enter clock more than 100Mhz ,(in sim), the engine don't work as well .. all output are wrong

[Altera_Forum]

Ah. 

Sorry, I misread you. You're having timing errors in gate level simulation.  Well, my first suggestion would be: use TimeQuest instead of the Classical Timming Analyzer.

[Altera_Forum]

i used it .. and i have the same error

[Altera_Forum]

Well.. I have seen TimeQuest fail to detect timing violations that only showed up in gate level simulations. 

That said, it's very rare and I'm not 100% sure that it wasn't an user error (poorly constrained design).  So, bunch of suggestions Even in TimeQuest, the fmax report isn't meant to be 100% reliable. Did you constrain your design to 170 MHz?  Is that the only clock in your design?  Did you constrain your inputs and outputs?

[Altera_Forum]

do you have a load of aynchrnous logic? neither timing analyser can give you an FMAx for that.