generate square waveform using DAC in Altera DE0 Kit

[Altera_Forum]

Dear All, 

 I'm new to Altera DE0 Kit.  Please let me know complete solution how to download & verify the output in the DE0 board  i) To sense physical parameter such as temperature/pressure/flow etc., convert in to digital using ADC, interface to PLD and display.  ii) To generate ramp/square waveform using DAC.  I have to use VHDL coding.  please also let me know any link to these projects on urgent basis.  Thanks in advance!

[Altera_Forum]

--- Quote Start ---   Please let me know complete solution how to download & verify the output in the DE0 board  ...  please also let me know any link to these projects on urgent basis.   --- Quote End ---  Terasic has plenty of design material for all of their boards, and some of your questions will be answered there;  http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=139&no=593  Note that you are unlikely to get help on this forum without first showing you have tried, and adding a sense of urgency to your request does not help. Once you have read through the Terasic material and have tried some VHDL design, some back and ask questions about any specific problems you have.  Cheers, Dave

[Altera_Forum]

Hallo! 

For simple digital design, verification of the logic in ALTERA DE0 is done. I've written VHDL code for square wave generation using DAC(Digital to Analog Converter). What all the components and files required to check the output on Cathode Required Oscilloscope. How about generation of User constrained file in ALTERA.  Please let me know the implementation part in ALTERA DE0 kit.  Thanks all in advance!

[Altera_Forum]

--- Quote Start ---   For simple digital design, verification of the logic in ALTERA DE0 is done.   --- Quote End ---  What is done? Simulation, synthesis or both?    --- Quote Start ---   I've written VHDL code for square wave generation using DAC(Digital to Analog Converter). What all the components and files required to check the output on Cathode Required Oscilloscope.   --- Quote End ---  You can program the FPGA and look at the signal with an oscilloscope. If you have a sampling oscilloscope with more bits and wider bandwidth than your DAC, then you can capture a block of samples, and analyze it to see if your DAC meets specifications.    --- Quote Start ---   How about generation of User constrained file in ALTERA.  Please let me know the implementation part in ALTERA DE0 kit.   --- Quote End ---  You would need to constrain the clock(s) and clock-to-output delays to the DAC. The timing requirements that the FPGA must meet are defined in the DAC datasheet. However, if you are using a DAC on the DE0, then Terasic should have an example constraints file.  Cheers, Dave